US4779232A
Expired / Lapsed
US
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Partial write control apparatus
Assignee: Hitachi Ltd
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Filing: 1987-05-20
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Granted: 1988-10-18
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Expires: 2007-05-20
Abstract
Abstract In a partial write control apparatus for a memory having a high speed operation mode such as a nibble mode or a page mode, when a partial write request for a plurality of words including those which require partial write is received, a memory control signal generator causes the memory to read successively all the words requiring partial write in a single high speed operation mode read cycle. A merging circuit merges those portions of the read-out words which need no alteration with write data and forms a group of updated complete words. Then, the memory control signal generator causes the memory to write successively these words in a single high speed operation mode write cycle.
Inventors
- 👤 Hidetada Fukunaka
- 👤 Koichi Ikeda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 04:57
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1015; G11C7/1018; G11C7/1021
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
234 words
A partial write control apparatus for a memory which has a number of locations each for storing an access unit of data and identified by an address and is provided with a high speed operation mode permitting successive accesses to a plurality of locations in a single access cycle, comprising: means for receiving request information requesting writing specified data into a plurality of specified locations one of which at least requires partial write; means responsive to said request information for supplying said memory with control signals for causing a single read cycle in said high speed operation mode to take place for successively reading out of all of the locations requiring partial write, and subsequently with control signals for causing a single write cycle in said high speed operation mode to take place for successively writing into all of said specified locations; means responsive to said request information for supplying said memory with address information for said read cycle and subsequently with address information for said write cycle; and merging means connected to receive said specified data and data read out of the memory in said read cycle and responsive to said request information for merging said specified data with portions not to be altered of the data read out in said read cycle to form a group of complete access units of data to be written into the memory in said write cycle.
Claim 2
Dependent Claim
234 words
A partial write control apparatus for a memory which has a number of locations each for storing an access unit of data and identified by an address and is provided with a high speed operation mode permitting successive accesses to a plurality of locations in a single access cycle, comprising: means for receiving request information requesting writing specified data into a plurality of specified locations one of which at least requires partial write; means responsive to said request information for supplying said memory with control signals for causing a single read cycle in said high speed operation mode to take place for successively reading out of all of the locations requiring partial write, and subsequently with control signals for causing a single write cycle in said high speed operation mode to take place for successively writing into all of said specified locations; means responsive to said request information for supplying said memory with address information for said read cycle and subsequently with address information for said write cycle; and merging means connected to receive said specified data and data read out of the memory in said read cycle and responsive to said request information for merging said specified data with portions not to be altered of the data read out in said read cycle to form a group of complete access units of data to be written into the memory in said write cycle.
Claim 3
Dependent Claim
66 words
A partial write control apparatus as claimed in claim 1, wherein said merging means includes a plurality of registers each for holding an access unit of data, means for storing said specified data into the corresponding portions of said registers and means for storing the portions not to be altered of the data read out in said read cycle into the corresponding portions of said registers.
Claim 4
Dependent Claim
30 words
A partial write control apparatus as claimed in claim 1, wherein said memory comprises a plurality of dynamic RAM elements, and said high speed operation mode is a nibble mode.
Claim 5
Dependent Claim
30 words
A partial write control apparatus as claimed in claim 1, wherein said memory comprises a plurality of dynamic RAM elements, and said high speed operation mode is a page mode.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-10-18 | 1992-04-18 | 1992-10-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-10-18 | 1996-04-18 | 1996-10-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-10-18 | 2000-04-18 | 2000-10-18 | $7700.00 | Window Closed / Lapsed |