US4879685A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device with internal array transfer capability
Assignee: Fujitsu Ltd
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Filing: 1989-02-16
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Granted: 1989-11-07
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Expires: 2009-02-16
Abstract
Abstract A semiconductor memory device includes, a plurality of word lines, a plurality of bit lines and a plurality of memory cells each connected between the word lines and the bit lines at each intersection of the word lines and bit lines. A plurality of sense amplifiers, each connected to each pair of bit lines, are for amplifying a difference in potential between each of the bit lines; a plurality of bit line reset circuits, each connected to each pair of the bit lines, the difference in potential being held during the read/write cycles. A transfer mode setting circuit is for optionally selecting a first word line and thereafter selecting a second word line, and for simultaneously reading out data in each memory cell connected to the first word line onto each bit line and thereafter simultaneously writing data on each bit line amplified by the sense amplifier into each corresponding memory cell connected to the second word line.
Inventors
- 👤 Yoshihiro Takemae
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 07:29
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C7/00; G11C8/00; G11C8/04
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
247 words
A semiconductor memory device, comprising: a plurality of word lines; a plurality of bit lines; a memory cell array, including: a plurality of memory cells connected between said word lines and said bit lines at intersections of said word lines and bits lines; and a plurality of sense amplifiers, each connected to a pair of bit lines, for amplifying a difference in potential between respective said bit lines; a plurality of bit line reset means, each connected to a pair of said bit lines, for resetting all said bit lines to a reset potential both before and after a read/write cycle; and transfer control means for arbitrarily selecting a first word line and thereafter selecting a second word line, and for simultaneously reading out data in each memory cell within the array connected to said first word line to each bit line and thereafter simultaneously writing data in each bit line amplified by said sense amplifier to each corresponding memory cell within the array connected to said second word line and producing a parallel data transfer, within the array, from memory cells corresponding to the first word line to memory cells corresponding to the second word line, said transfer control means including inhibit means, connected to said bit line reset means, for inhibiting resetting of said bit lines during the parallel data transfer, directly writing potentials developed on said bit lines during the reading out into memory cells connected to said second word line during the writing.
Claim 2
Dependent Claim
247 words
A semiconductor memory device, comprising: a plurality of word lines; a plurality of bit lines; a memory cell array, including: a plurality of memory cells connected between said word lines and said bit lines at intersections of said word lines and bits lines; and a plurality of sense amplifiers, each connected to a pair of bit lines, for amplifying a difference in potential between respective said bit lines; a plurality of bit line reset means, each connected to a pair of said bit lines, for resetting all said bit lines to a reset potential both before and after a read/write cycle; and transfer control means for arbitrarily selecting a first word line and thereafter selecting a second word line, and for simultaneously reading out data in each memory cell within the array connected to said first word line to each bit line and thereafter simultaneously writing data in each bit line amplified by said sense amplifier to each corresponding memory cell within the array connected to said second word line and producing a parallel data transfer, within the array, from memory cells corresponding to the first word line to memory cells corresponding to the second word line, said transfer control means including inhibit means, connected to said bit line reset means, for inhibiting resetting of said bit lines during the parallel data transfer, directly writing potentials developed on said bit lines during the reading out into memory cells connected to said second word line during the writing.
Claim 3
Dependent Claim
57 words
A semiconductor memory device as claimed in claim 1, wherein said transfer control means comprises a transfer enable signal generating circuit, connected to said bit line reset means which generates a transfer enable signal in response to an input transfer signal to hold the potential between each of said bit lines using said bit line reset means.
Claim 4
Dependent Claim
49 words
A semiconductor memory device as claimed in claim 2, wherein said transfer control means further comprises a transfer word line drive circuit, operatively connected to said word lines and said transfer enable generating circuit, which generates a transfer word drive signal to select said first and second word lines.
Claim 5
Dependent Claim
49 words
A semiconductor memory device as claimed in claims 1, 2 or 3, wherein said transfer control means further comprises a word decoder, connected to said word lines and said transfer word line drive circuit, which selects said first and second word lines based on said transfer word drive signal.
Claim 6
Dependent Claim
69 words
A semiconductor memory device as claimed in claim 2, wherein said transfer enable signal has a low level and said bit line reset means comprises a MOS transistor connected to each bit line, each MOS transistor having a gate receiving said transfer enable signal and each of said MOS transistors being cut off when the low level of said transfer enable signal is input to each of said gates.
Claim 7
Dependent Claim
54 words
A semiconductor device as claimed in claim 1, further comprising decoder means for providing a first selection signal for the first word line in response to a first address and for providing a second selection signal for an adjacent word line in response to the first address and an adjacent word line selection signal.
Claim 8
Dependent Claim
47 words
A semiconductor device as claimed in claim 1, further comprising decoder means for providing a first selection signal for the first word line in response to a first address and for providing a second selection signal for the second word line in response to a second address.
Claim 9
Dependent Claim
74 words
A semiconductor memory device, comprising: transfer enabling means for signalling a scrolling transfer; a memory cell array having multiple memory cells with bit lines; and transfer control means, operatively connected to said transfer enabling means and said memory cell array, for controlling simultaneous parallel transfer of the contents of the multiple memory cells internally between the multiple memory cells within the array using the bit lines for memory cell content storage during the transfer.
Claim 10
Dependent Claim
74 words
A semiconductor memory device, comprising: transfer enabling means for signalling a scrolling transfer; a memory cell array having multiple memory cells with bit lines; and transfer control means, operatively connected to said transfer enabling means and said memory cell array, for controlling simultaneous parallel transfer of the contents of the multiple memory cells internally between the multiple memory cells within the array using the bit lines for memory cell content storage during the transfer.
Claim 11
Dependent Claim
17 words
A semiconductor device as claimed in claim 8, wherein the parallel transfer occurs within one memory cycle.
Claim 12
Dependent Claim
199 words
A semiconductor memory device, comprising: a plurality of word lines; a plurality of bit lines; a plurality of memory cells respectively connected between said word lines and said bit lines at intersections of said word lines and bit lines; a plurality of sense amplifiers, each connected to a pair of bit lines, for amplifying a difference in potential between respective said bit lines; a plurality of bit line reset means, each connected to a pair of said bit lines, for holding the difference in potential during a combined read/write memory cycle; and transfer control means for arbitrarily selecting a first word line and thereafter selecting a second word line, and for simultaneously, during one combined read/write memory cycle, reading out data in each memory cell connected to said first word line onto each bit line and thereafter also simultaneously writing data on each bit line amplified by said sense amplifiers to each corresponding memory cell connected to said second word line using said bit lines to hold cell contents during the reading and writing, said transfer control means selecting any one of said word lines as either said first or second word line during each combined read/write memory cycle.
Claim 13
Dependent Claim
199 words
A semiconductor memory device, comprising: a plurality of word lines; a plurality of bit lines; a plurality of memory cells respectively connected between said word lines and said bit lines at intersections of said word lines and bit lines; a plurality of sense amplifiers, each connected to a pair of bit lines, for amplifying a difference in potential between respective said bit lines; a plurality of bit line reset means, each connected to a pair of said bit lines, for holding the difference in potential during a combined read/write memory cycle; and transfer control means for arbitrarily selecting a first word line and thereafter selecting a second word line, and for simultaneously, during one combined read/write memory cycle, reading out data in each memory cell connected to said first word line onto each bit line and thereafter also simultaneously writing data on each bit line amplified by said sense amplifiers to each corresponding memory cell connected to said second word line using said bit lines to hold cell contents during the reading and writing, said transfer control means selecting any one of said word lines as either said first or second word line during each combined read/write memory cycle.
References Cited (Backward Citations)
US3898632A
Cited
US4162541A
Cited
US4386421A
Cited
US4395764A
Cited
US4429375A
Cited
US4412313A
Cited
US4602251A
Cited
US4661812A
Cited
US4644502A
Cited
US4639890A
Cited
US4688197A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-11-06 | 1993-05-08 | 1993-11-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-11-06 | 1997-05-08 | 1997-11-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-11-06 | 2001-05-08 | 2001-11-07 | $7700.00 | Window Closed / Lapsed |