Semiconductor memory device typically used as a video ram

Claim 2

A semiconductor memory device operatively connectable to receive an external address and operatively connectable to an external circuit, comprising: a memory cell array accessible by the external circuit; an addressing circuit, operatively connected to said memory cell array and operatively connectable to receive the external address, for effecting an access operation to each bit of said memory cell array in accordance with the external address; an internal address generating circuit for sequentially generating row address outputs including a plurality of bit data; an address switching circuit, operatively connected to said internal address generating circuit and operatively connectable to receive the external address, for switching between the row address outputs from said internal address generating circuit and the external address; a plurality of shift registers, operatively connected to said memory cell array and said internal address generating circuit, each of said plurality of shift registers storing a plurality of bit data read out in parallel from said memory cell array in accordance with said row address outputs; and a serial control circuit, operatively connected to said plurality of shift registers, for controlling each of said plurality of shift registers so that each of said plurality of shift registers effects a shift operation to serially and continuously output data, and when said memory cell array is not accessed by the external circuit during a time period in which a plurality of bit data corresponding to one of said row address outputs is serially output from one of said plurality of shift registers, said serial control circuit effects a parallel readout operation of a plurality of bit data corresponding to a next one of said row address outputs from said memory cell array and loads the data thus read out to another one of said plurality of shift registers.

Claim 3

A semiconductor memory device according to claim 1, operatively connectable to receive a random access signal, wherein the external circuit accesses said memory cell array by using the external address and the random access signal, and wherein said address switching circuit switches between said row address outputs from said internal address generating circuit and the external address.

Claim 4

A semiconductor memory device according to claim 1, wherein the external circuit supplies serial clock signals, wherein each of said plurality of shift registers registers effects a shift operation in accordance with the serial clock signals supplied thereto from the external circuit, and wherein said serial control circuit counts the serial clock signals to generate the increment clock signals which are counted by said internal address generating circuit to generate said row address outputs.

Claim 5

A semiconductor memory device according to claim 1, wherein the external address includes an external column address data, wherein said addressing circuit comprises: a row decoder, operatively connected to said address switching circuit, for decoding said row address outputs from said address switching circuit; and a column decoder, operatively connected to receive the external address, for decoding the external column address data included in the external address.

Claim 6

A semiconductor memory device according to claim 4, wherein the external address further includes external row address data, and wherein said semiconductor memory device further comprises: a column address buffer operatively connected to said column decoder and operatively connected to receive the external column address data; and a row address buffer operatively connected to said row decoder and operatively connected to receive the external row address data and the row address outputs.

Claim 7

A semiconductor memory device according to claim 1, wherein said serial control circuit provides a register selecting signal and wherein said semiconductor memory device further comprises a selecting circuit, operatively connected to said shift registers, for selecting one of said plurality of shift registers in which serial data is input or output, in accordance with the register selecting signal supplied by said serial control circuit.

Claim 8

A semiconductor memory device according to claim 6, wherein said selecting circuit transmits serial output data of said selected one of said shift registers to the external circuit or transmits serial input data from the external circuit to said selected one of said shift registers.

Claim 9

A semiconductor memory device operatively connectable to receive an external address and operatively connectable to an external circuit, comprising: a memory cell array, operatively connected to the external circuit, being accessed by the external circuit; an addressing circuit, operatively connected to said memory cell array, for effecting an access operation to each bit of said memory cell array in accordance with the external address; an internal address generating circuit for sequentially generating row address outputs; an address switching circuit, operatively connected to said internal address generating circuit and operatively connectable to receive the external address, for switching between said row address outputs from said internal address generating circuit and the external address; a plurality of shift registers, operatively connected to said memory cell array and operatively connected to said internal address generating circuit, each of said shift registers storing a plurality of bit data to be written-in parallel into said memory cell array in accordance with said row address outputs; and a serial control circuit, operatively connected to said plurality of shift registers, for controlling each of said plurality of shift registers so that each of said shift registers effects a shift operation to serially and continuously record data therein, and when said memory cell array is not accessed by the external circuit during a time period in which a plurality of bit data corresponding to one of said row address outputs is serially input into one of said plurality of shift registers from the external circuit, said serial control circuit effects a parallel write-in operation of a plurality of bit data, corresponding to a next one of said row address outputs, to said memory cell array.

Claim 10

A semiconductor memory device operatively connectable to receive an external address and operatively connectable to an external circuit, comprising: a memory cell array, operatively connected to the external circuit, being accessed by the external circuit; an addressing circuit, operatively connected to said memory cell array, for effecting an access operation to each bit of said memory cell array in accordance with the external address; an internal address generating circuit for sequentially generating row address outputs; an address switching circuit, operatively connected to said internal address generating circuit and operatively connectable to receive the external address, for switching between said row address outputs from said internal address generating circuit and the external address; a plurality of shift registers, operatively connected to said memory cell array and operatively connected to said internal address generating circuit, each of said shift registers storing a plurality of bit data to be written-in parallel into said memory cell array in accordance with said row address outputs; and a serial control circuit, operatively connected to said plurality of shift registers, for controlling each of said plurality of shift registers so that each of said shift registers effects a shift operation to serially and continuously record data therein, and when said memory cell array is not accessed by the external circuit during a time period in which a plurality of bit data corresponding to one of said row address outputs is serially input into one of said plurality of shift registers from the external circuit, said serial control circuit effects a parallel write-in operation of a plurality of bit data, corresponding to a next one of said row address outputs, to said memory cell array.

Claim 11

A memory system, operatively connected to receive an external address and operatively connectable to an external circuit, for effecting random access and serial access independently, said memory system comprising: a plurality of semiconductor memory devices providing serial output data; an external shift register having a number of circuit stages equal to the number of said semiconductor memory devices, said memory system providing one of the operations of reading in parallel the serial output data from said semiconductor memory devices into said circuit stages of said external shift register and writing in parallel data stored in said external shift register into said semiconductor memory devices, said external shift register performing one of the operations of serially ouputting data stored therein and serially inputting data thereto, respectively; each of said semiconductor memory devices comprising: a memory cell array, operatively connected to the external circuit, said memory cell array being accessed by the external circuit; an addressing circuit, operatively connected to said memory cell array, for effecting an access operation to each bit of said memory cell array in accordance with the external address; an internal address generating circuit for sequentially generating row address outputs; an address switching circuit, operatively connected to said internal address generating circuit and operatively connected to receive the external address, for switching between the row address outputs from said internal address generating circuit and the external address; a plurality of shift registers, operatively connected to said memory cell array, each of said shift registers storing a plurality of bit data read out in parallel from or written into said memory cell array in accordance with said row address outputs; and a serial control circuit for controlling said shift registers, each of said shift registers performing a shift operation to serially and continuously output or write-in data, and when said memory cell array is not accessed by the external circuit during a time period in which a plurality of bit data corresponding to a row address is serially output from or written into one of said plurality of shift registers, said serial control circuit effects a parallel readout or write-in operation of a plurality of bit data corresponding to the next row address from said memory cell array or to said memory cell array, respectively.

Claim 12

A memory system, operatively connected to receive an external address and operatively connectable to an external circuit, for effecting random access and serial access independently, said memory system comprising: a plurality of semiconductor memory devices providing serial output data; an external shift register having a number of circuit stages equal to the number of said semiconductor memory devices, said memory system providing one of the operations of reading in parallel the serial output data from said semiconductor memory devices into said circuit stages of said external shift register and writing in parallel data stored in said external shift register into said semiconductor memory devices, said external shift register performing one of the operations of serially ouputting data stored therein and serially inputting data thereto, respectively; each of said semiconductor memory devices comprising: a memory cell array, operatively connected to the external circuit, said memory cell array being accessed by the external circuit; an addressing circuit, operatively connected to said memory cell array, for effecting an access operation to each bit of said memory cell array in accordance with the external address; an internal address generating circuit for sequentially generating row address outputs; an address switching circuit, operatively connected to said internal address generating circuit and operatively connected to receive the external address, for switching between the row address outputs from said internal address generating circuit and the external address; a plurality of shift registers, operatively connected to said memory cell array, each of said shift registers storing a plurality of bit data read out in parallel from or written into said memory cell array in accordance with said row address outputs; and a serial control circuit for controlling said shift registers, each of said shift registers performing a shift operation to serially and continuously output or write-in data, and when said memory cell array is not accessed by the external circuit during a time period in which a plurality of bit data corresponding to a row address is serially output from or written into one of said plurality of shift registers, said serial control circuit effects a parallel readout or write-in operation of a plurality of bit data corresponding to the next row address from said memory cell array or to said memory cell array, respectively.