US4162541A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for overscribing binary data of a selected polarity into a semiconductor store
Assignee: Xerox Corp
•
Filing: 1977-02-17
•
Granted: 1979-07-24
•
Expires: 1997-02-17
Abstract
Abstract Apparatus which reduces the cycle sequences of a buffer in order to meet high data merge rates by selective control of the chip enable inputs of a plurality of memory chips. During a write ones merge cycle, data patterns from a data-in register control the chip enable inputs of the memory chips and, simultaneously, a common data input line connected to the memory chips is held at logic one. After allowing sufficient time for address decoding of selected memory chips, a common memory write line of the memory chips is enabled to write ones into the selected words of the selected memory chips, while all the other memory chips are undisturbed since their chip enable inputs have not been activated.
Inventors
- 👤 David Hartke
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 00:32
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/42
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
192 words
Apparatus for overscribing binary data of a selected polarity into a semiconductor store, comprising: a source of a data signal of a selected electrical polarity; a semiconductor store including an array of memory chips each enabled by a corresponding chip enable signal, each memory chip including a read/write terminal for selecting the direction of data transfer thereby and a data-in terminal connected to said source for receiving said data signal of said selected polarity; addressing means including signal generating means for providing a write signal to said read/write terminals in lagging relationship relative to said chip enable signals for selecting storage locations for said data signal within said memory chips for write-in of the data signal at those selected locations; means for generating a common logic signal; a data register having stored therein a plurality of binary signals; and a plurality of gates each connected to provide said chip enable signals to selected ones of said memory chips in response to receipt of one of said binary signals from said data register and said logic signal for enabling said memory chips to selectively store said data signal of said selected electrical polarity.
Claim 2
Dependent Claim
192 words
Apparatus for overscribing binary data of a selected polarity into a semiconductor store, comprising: a source of a data signal of a selected electrical polarity; a semiconductor store including an array of memory chips each enabled by a corresponding chip enable signal, each memory chip including a read/write terminal for selecting the direction of data transfer thereby and a data-in terminal connected to said source for receiving said data signal of said selected polarity; addressing means including signal generating means for providing a write signal to said read/write terminals in lagging relationship relative to said chip enable signals for selecting storage locations for said data signal within said memory chips for write-in of the data signal at those selected locations; means for generating a common logic signal; a data register having stored therein a plurality of binary signals; and a plurality of gates each connected to provide said chip enable signals to selected ones of said memory chips in response to receipt of one of said binary signals from said data register and said logic signal for enabling said memory chips to selectively store said data signal of said selected electrical polarity.
Claim 3
Dependent Claim
15 words
Apparatus according to claim 1 wherein: said binary data is of a binary one polarity.
References Cited (Backward Citations)
US3292151A
Cited
US3781826A
Cited
US3895357A
Cited
US4029947A
Cited
US3944983A
Cited
US4005393A
Cited
US3967251A
Cited
US4016545A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-07-23 | 1983-01-22 | 1983-07-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-07-23 | 1987-01-22 | 1987-07-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-07-23 | 1991-01-22 | 1991-07-24 | $7700.00 | Window Closed / Lapsed |