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US5696395A Expired / Lapsed US ⏱️ 0.0 years remaining

Dynamic random access memory with fin-type stacked capacitor

Assignee: Industrial Technology Research Institute
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Filing: 1996-08-26
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Granted: 1997-12-09
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Expires: 2016-08-26
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Abstract

Abstract A method is described for fabricating a dynamic random access memory having a high capacitance fin-type stacked capacitor. The method begins by selectively forming relatively thick field oxide areas on the surface of a semiconductor substrate while leaving device areas for fabrication of field effect devices. A gate dielectric layer is formed on the substrate in the device areas. A relatively thick first layer of polysilicon is deposited on the field oxide areas and the device areas. Portions of the first polysilicon layer is removed while leaving portions thereof for the gate structure in the device areas, and portions over the field oxide areas. Source/drain structures are formed within the device areas of said semiconductor substrate associated with the gate structures. A first insulator layer composed at least in part of silicon nitride is formed over the device and field oxide areas. The fin-type stacked capacitors are now formed by first depositing a second polysilicon layer over the device and field oxide areas. Alternating layers of polysilicon and insulator are deposited over the device and field oxide areas with a first polysilicon layer being contact to the device areas for electrical contact and the last polysilicon layer being the topmost of the alternating layers. The stack of alternating polysilicon and insulator layers are now patterned to form the basis of the stacked capacitors. The exposed edges of the insulator layers are controlably and laterally isotropic etched to increase the planned surface area of the capacitor by forming fin-type structures. A fourth polysilicon layer is deposited over the device and field oxide areas to complete the lower electrode of the stacked capacitor. A capacitor dielectric layer is formed over the lower electrode of the stacked capacitor and the top polysilicon electrode layer is deposited thereover to complete the stacked capacitors.

Inventors

  • 👤 Horng-Huei Tseng

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 03:18
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/30; H10B12/31; H10B12/318; H10D; H10D1/00; H10D1/01; H10D1/041; H10D1/042; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10D1/714; Y; Y10; Y10S; Y10S438/00; Y10S438/967

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 297 words
A stacked capacitor structure, dynamic random access memory, (DRAM), device, with a fin-type shaped, polysilicon lower electrode, on a semiconductor structure, comprising: field oxide regions in a semiconductor substrate; a device region in said semiconductor substrate, between said field oxide regions; a gate dielectric layer, on said device region; a first polysilicon gate structure, on said gate dielectric layer, with an overlying cap insulator layer, and a polysilicon interconnecting structure, with an overlying cap insulator layer, on a field oxide region; insulator spacers on the sidewalls of said polysilicon gate structure, and on said polysilicon interconnecting structure; source and drain regions in said device region of said semiconductor substrate, in an area of said device region not covered by said polysilicon gate structure; a composite dielectric layer, patterned to leave said source and drain regions open, in said device region, where electrical contact is desired to said stacked capacitor structure; said fin-type shaped, polysilicon lower electrode, of said stacked capacitor structure, contacting one of said source and drain regions, in said device region, and partially overlying said composite dielectric layer, on said polysilicon gate structure, and partially overlying said composite dielectric layer on said polysilicon interconnecting structure, with said fin-type shaped, polysilicon lower electrode, constructed of, a series of lateral, polysilicon fins, between about 7000 to 14000 Angstroms, in length, with the bottom polysilicon fin, contacting one of said source and drain regions, a series of insulator core layers, between about 5000 to 10000 Angstroms, in length, residing in the center, between underlying and overlying said lateral, polysilicon fins, a connecting polysilicon layer overlying and traversing exposed surfaces of said lateral, polysilicon fins, and exposed surfaces of said insulator core layers; a capacitor dielectric layer on said fin-shaped, polysilicon lower electrode; and a upper polysilicon electrode structure.
Claim 2
Dependent Claim 297 words
A stacked capacitor structure, dynamic random access memory, (DRAM), device, with a fin-type shaped, polysilicon lower electrode, on a semiconductor structure, comprising: field oxide regions in a semiconductor substrate; a device region in said semiconductor substrate, between said field oxide regions; a gate dielectric layer, on said device region; a first polysilicon gate structure, on said gate dielectric layer, with an overlying cap insulator layer, and a polysilicon interconnecting structure, with an overlying cap insulator layer, on a field oxide region; insulator spacers on the sidewalls of said polysilicon gate structure, and on said polysilicon interconnecting structure; source and drain regions in said device region of said semiconductor substrate, in an area of said device region not covered by said polysilicon gate structure; a composite dielectric layer, patterned to leave said source and drain regions open, in said device region, where electrical contact is desired to said stacked capacitor structure; said fin-type shaped, polysilicon lower electrode, of said stacked capacitor structure, contacting one of said source and drain regions, in said device region, and partially overlying said composite dielectric layer, on said polysilicon gate structure, and partially overlying said composite dielectric layer on said polysilicon interconnecting structure, with said fin-type shaped, polysilicon lower electrode, constructed of, a series of lateral, polysilicon fins, between about 7000 to 14000 Angstroms, in length, with the bottom polysilicon fin, contacting one of said source and drain regions, a series of insulator core layers, between about 5000 to 10000 Angstroms, in length, residing in the center, between underlying and overlying said lateral, polysilicon fins, a connecting polysilicon layer overlying and traversing exposed surfaces of said lateral, polysilicon fins, and exposed surfaces of said insulator core layers; a capacitor dielectric layer on said fin-shaped, polysilicon lower electrode; and a upper polysilicon electrode structure.
Claim 3
Dependent Claim 22 words
The stacked capacitor structure of claim 1, wherein the thickness of each said polysilicon fin is between about 500 to 1500 Angstroms.
Claim 4
Dependent Claim 34 words
The stacked capacitor structure of claim 1, wherein the composition of each said insulator core layer is silicon oxide, the thickness of each said insulator core layer is between about 1000 to 2000 Angstroms.
Claim 5
Dependent Claim 22 words
The stacked capacitor structure of claim 1, wherein said capacitor dielectric layer is composed of silicon oxide, silicon nitride and silicon oxide.

References Cited (Backward Citations)

US4700457A Cited
US4742018A Cited
US5572053A Cited
JPH01154552A Cited
US5126810A Cited
US5156993A Cited
US5262662A Cited
US5134085A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2000-12-08 2001-06-09 2001-12-09 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2004-12-08 2005-06-09 2005-12-09 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2008-12-08 2009-06-09 2009-12-09 $7700.00 Window Closed / Lapsed

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