Memory element and method of operation thereof

Claim 2

A memory comprising: a first stored charge element having first and second terminals; a first memory access node coupled to the first terminal of the first stored charge element; a first charge input path having a second memory access node, the first charge input path being a charge path into the second terminal of the first stored charge element and having a substantially definite voltage drop threshold from the second memory access node to the second terminal of the first stored charge element above which conduction occurs with no significant deterioration over time and below which significant conduction does not occur; and a first charge output path having a third memory access node, the first charge output path being a charge path from the second terminal of the first stored charge element and having a substantially definite voltage drop threshold from the second terminal of the first stored charge element to the third memory access node above which conduction occurs with no significant deterioration over time and below which significant conduction does not occur, the respective voltage drop thresholds of the first charge input path and the first charge output path being unequal; wherein at least one of the first, second and third memory access nodes is a bit node.

Claim 3

A memory as in claim 1 wherein the stored charge element is a discrete integrated circuit capacitor.

Claim 4

A memory as in claim 1 wherein the stored charge element is gate capacitance of a MOSFET.

Claim 5

A memory as in claim 1 wherein the first charge input path and the first charge output path are opposite directions through a bi-directional voltage dropping element.

Claim 6

A memory as in claim 4 wherein: the bi-directional voltage dropping element is a bi-directional voltage dropping device; and the bi-directional voltage dropping device has a first terminal coupled to the second terminal of the stored charge element and a second terminal that includes the second and third memory access nodes.

Claim 7

A memory as in claim 5 wherein the bi-directional voltage dropping device is a Zener diode having a forward direction and a reverse direction corresponding to the opposite directions through the bi-directional voltage dropping device.

Claim 8

A memory as in claim 4 wherein: the first charge input path through the bi-directional voltage dropping element is a first voltage dropping device having one terminal coupled to the second terminal of the first stored charge element and a second terminal that is the second memory access node; and the first charge output path through the bi-directional voltage dropping element is a second voltage dropping device having one terminal coupled to the second terminal of the first stored charge element and a second terminal that is the third memory access node.

Claim 9

A memory as in claim 7 wherein the first and second voltage dropping devices are respective diodes and the substantially definite voltage drop thresholds are voltage drop thresholds in forward directions through the diodes.

Claim 10

A memory as in claim 1 wherein: the first stored charge element, the first charge input path, and the first charge output path form in combination a first dynamic memory cell; and the second and third memory access nodes are in unity as a terminal of the first dynamic memory cell.

Claim 11

A memory as in claim 9 further comprising a second dynamic memory cell having: a second stored charge element having first and second terminals; a fourth memory access node coupled to the first terminal of the second stored charge element; a second charge input path having a fifth memory access node, the second charge input path being a charge path into the second terminal of the second stored charge element and having a substantially definite voltage drop threshold from the fifth memory access node to the second terminal of the second stored charge element above which conduction occurs with no significant deterioration over time and below which significant conduction does not occur; and a second charge output path that includes the fifth memory access node, the second charge output path being a charge path from the second terminal of the second stored charge element and having a substantially definite voltage drop threshold from the second terminal of the second stored charge element to the fifth memory access node above which conduction occurs with no significant deterioration over time and below which significant conduction does not occur, the respective voltage drop thresholds of the second charge input path and the second charge output path being unequal; wherein at least one of the fourth and fifth memory access nodes is a bit node, and wherein the first, second, fourth and fifth nodes are interconnected in any manner provided the first and second memory access nodes are not interconnected, and further provided the fourth and fifth memory access nodes are not interconnected.

Claim 12

A memory as in claim 10 wherein the first and fourth memory access nodes are respectively portions of a word select line, and the second and fifth memory access nodes are respective portions of different column bit lines.

Claim 13

A memory as in claim 10 wherein the first and fourth memory access nodes are respectively portions of different word select lines, and the second and fifth memory access nodes are respective portions of a column bit line.

Claim 14

A memory as in claim 1 wherein: the first stored charge element, the first charge input path, and the first charge output path form in combination a first dynamic memory cell; and the second and third memory access nodes are separate terminals of the first dynamic memory cell.

Claim 15

A memory as in claim 13 further comprising a second dynamic memory cell having: a second stored charge element having first and second terminals; a fourth memory access node coupled to the first terminal of the second stored charge element; a second charge input path having a fifth memory access node, the second charge input path being a charge path into the second terminal of the second stored charge element and having a substantially definite voltage drop threshold from the fifth memory access node to the second terminal of the second stored charge element above which conduction occurs with no significant deterioration over time and below which significant conduction does not occur; and a second charge output path having a sixth memory access node, the second charge output path being a charge path from the second terminal of the second stored charge element and having a substantially definite voltage drop threshold from the second terminal of the second stored charge element to the sixth memory access node above which conduction occurs with no significant deterioration over time and below which significant conduction does not occur, the respective voltage drop thresholds of the second charge input path and the second charge output path being unequal; wherein at least one of the fourth, fifth and sixth memory access nodes is a bit node, and wherein the first, second, third, fourth, fifth and sixth memory access nodes are interconnected in any manner provided the first memory access node is not interconnected with either of the second and third memory access nodes, and further provided the fourth memory access node is not interconnected with either of the fifth and sixth memory access nodes.

Claim 16

A memory as in claim 14 wherein the first and fourth memory access nodes are respectively portions of a word select line, the second and fifth memory access nodes are respective portions of different charge column bit lines, and the third and sixth memory access nodes are respective portions of different discharge column bit lines.

Claim 17

A memory as in claim 15 wherein the charge column bit lines are bit read lines and the discharge column bit lines are bit write lines.

Claim 18

A memory as in claim 14 wherein the first and fourth memory access nodes are respectively portions of different word select lines, the second and fifth memory access nodes are respective portions of a charge column bit line, and the third and sixth memory access nodes are respective portions of a discharge column bit line.

Claim 19

A memory element as in claim 17 wherein the charge column bit line is a bit read line and the discharge column bit line is a bit write line.

Claim 20

A memory as in claim 1 wherein a voltage V H across the stored charge element is indicative of a first logical state, a voltage V L across the stored charge element is indicative of a second logical state, the substantially definite voltage drop threshold of the first charge input path is represented by V I , and the substantially definite voltage drop threshold of the first charge output path is represented by V O , further comprising: means for establishing a voltage V 1C on the first memory access node and a voltage V 2C on the second memory access node, the voltages V 1C and V 2C being related approximately in accordance with the expression V 2C +V H ≧V I +V 1C ; means for establishing a voltage V 1D on the first memory access node and a voltage V 3D on the third memory access node, the voltages V 1D and V 3D being related approximately in accordance with the expression V 1D ≧V L +V O +V 3D ; and means for sensing perturbation in voltage on the second memory access node.

Claim 21

A memory as in claim 19 further comprising: means for establishing an idle voltage V 1X on the first memory access node, the voltages V 1X and V 2C being related approximately in accordance with the expression V 2C +V L ≦V I +V 1X , and the voltages V 1X and V 3D being related approximately in accordance with the expression V 1X ≦V H +V O +V 3D ; means for establishing an idle voltage V 2X on the second memory access node, the voltages V 1C and V 2X being related approximately in accordance with the expression V 2X +V L ≦V I +V 1C , and the voltages V 1D and V 2X being related approximately in accordance with the expression V 2X +V L ≦V I +V 1D ; and means for establishing an idle voltage V 3X on the third memory access node, the voltages V 1C and V 3X being related approximately in accordance with the expression V 1C ≦V H +V O +V 3X , and the voltages V 1D and V 3X being related approximately in accordance with the expression V 1D ≦V H +V O +V 3X .

Claim 22

A memory as in claim 20 wherein V H exceeds V L by not more than about half of V I +V O .

Claim 23

A memory comprising: a stored charge element having first and second terminals; a first memory access node coupled to the first terminal of the first stored charge element; a charge input path having a second memory access node, the charge input path being a charge path into the second terminal of the first stored charge element and having a substantially definite voltage drop threshold from the second memory access node to the second terminal of the first stored charge element above which conduction occurs with no significant deterioration over time and below which significant conduction does not occur; a charge output path having a third memory access node, the charge output path being a charge path from the second terminal of the first stored charge element and having a substantially definite voltage drop threshold from the second terminal of the first stored charge element to the third memory access node above which conduction occurs with no significant deterioration over time and below which significant conduction does not occur; and an amplifying valve having a control terminal coupled to the second terminal of the first stored charge element, a first current terminal coupled to the first access node, and a second current terminal coupled to a memory read node; wherein at least one of the first, second and third memory access nodes is a bit node.

Claim 24

A memory comprising: a stored charge element having first and second terminals; a first memory access node coupled to the first terminal of the first stored charge element; a charge input path having a second memory access node, the charge input path being a charge path into the second terminal of the first stored charge element and having a substantially definite voltage drop threshold from the second memory access node to the second terminal of the first stored charge element above which conduction occurs with no significant deterioration over time and below which significant conduction does not occur; a charge output path having a third memory access node, the charge output path being a charge path from the second terminal of the first stored charge element and having a substantially definite voltage drop threshold from the second terminal of the first stored charge element to the third memory access node above which conduction occurs with no significant deterioration over time and below which significant conduction does not occur; and an amplifying valve having a control terminal coupled to the second terminal of the first stored charge element, a first current terminal coupled to the first access node, and a second current terminal coupled to a memory read node; wherein at least one of the first, second and third memory access nodes is a bit node.

Claim 25

A memory comprising: a first stored charge element having first and second terminals; a first memory access node coupled to the first terminal of the first stored charge element; a first charge input path having a second memory access node, the first charge input path being a charge path into the second terminal of the first stored charge element and having a substantially definite voltage drop threshold from the second memory access node to the second terminal of the first stored charge element above which conduction occurs and below which significant conduction does not occur; and a first charge output path having a third memory access node, the first charge output path being a charge path from the second terminal of the first stored charge element and having a substantially definite voltage drop threshold from the second terminal of the first stored charge element to the third memory access node above which conduction occurs and below which significant conduction does not occur; wherein the first stored charge element, the first charge input path, and the first charge output path form in combination a first dynamic memory cell, the memory further comprising a word select line, first, second and third column bit lines, and a second dynamic memory cell having: a second stored charge element having first and second terminals; a fourth memory access node coupled to the first terminal of the second stored charge element; a second charge input path having a fifth memory access node, the second charge input path being a charge path into the second terminal of the second stored charge element and having a substantially definite voltage drop threshold from the fifth memory access node to the second terminal of the second stored charge element above which conduction occurs and below which significant conduction does not occur; and a second charge output path having a sixth memory access node, the second charge output path being a charge path from the second terminal of the second stored charge element and having a substantially definite voltage drop threshold from the second terminal of the second stored charge element to the sixth memory access node above which conduction occurs and below which significant conduction does not occur; wherein the first and fourth memory access nodes are coupled to the word select line, the second and sixth memory access nodes are coupled to the second column bit line, the third memory access node is coupled to the first column bit line, and the fifth memory access node is coupled to the third column bit line.

Claim 26

A memory comprising: a first stored charge element having first and second terminals; a first memory access node coupled to the first terminal of the first stored charge element; a first charge input path having a second memory access node, the first charge input path being a charge path into the second terminal of the first stored charge element and having a substantially definite voltage drop threshold from the second memory access node to the second terminal of the first stored charge element above which conduction occurs and below which significant conduction does not occur; and a first charge output path having a third memory access node, the first charge output path being a charge path from the second terminal of the first stored charge element and having a substantially definite voltage drop threshold from the second terminal of the first stored charge element to the third memory access node above which conduction occurs and below which significant conduction does not occur; wherein the first stored charge element, the first charge input path, and the first charge output path form in combination a first dynamic memory cell, the memory further comprising a word select line, first, second and third column bit lines, and a second dynamic memory cell having: a second stored charge element having first and second terminals; a fourth memory access node coupled to the first terminal of the second stored charge element; a second charge input path having a fifth memory access node, the second charge input path being a charge path into the second terminal of the second stored charge element and having a substantially definite voltage drop threshold from the fifth memory access node to the second terminal of the second stored charge element above which conduction occurs and below which significant conduction does not occur; and a second charge output path having a sixth memory access node, the second charge output path being a charge path from the second terminal of the second stored charge element and having a substantially definite voltage drop threshold from the second terminal of the second stored charge element to the sixth memory access node above which conduction occurs and below which significant conduction does not occur; wherein the first and fourth memory access nodes are coupled to the word select line, the second and sixth memory access nodes are coupled to the second column bit line, the third memory access node is coupled to the first column bit line, and the fifth memory access node is coupled to the third column bit line.

Claim 27

A memory as in claim 23 wherein a voltage V H across the first and second stored charge elements is indicative of a first logical state and a voltage V L across the first and second stored charge elements is indicative of a second logical state, further comprising: means for maintaining the second column bit line nominally offset from the first column bit by V H -V L ; and means for maintaining the third column bit line nominally offset from the second column bit by V H -V L .

Claim 28

A memory comprising: a stored charge element having first and second terminals; a first memory access node coupled to the first terminal of the first stored charge element; a charge input path having a second memory access node, the first charge input path being a charge path into the second terminal of the first stored charge element and having a substantially definite voltage drop threshold from the second memory access node to the second terminal of the first stored charge element above which conduction occurs and below which significant conduction does not occur; a charge output path having a third memory access node, the first charge output path being a charge path from the second terminal of the first stored charge element and having a substantially definite voltage drop threshold from the second terminal of the first stored charge element to the third memory access node above which conduction occurs and below which significant conduction does not occur; and a latch having an input/output terminal coupled to the second terminal of the stored charge element; wherein at least one of the first, second and third memory access nodes is a bit node, and the charge input path and the charge output path are opposite directions through a bi-directional voltage dropping element having a first terminal coupled to the second terminal of the stored charge device and a second terminal that includes the second and third memory access nodes.

Claim 29

A memory comprising: a stored charge element having first and second terminals; a first memory access node coupled to the first terminal of the first stored charge element; a charge input path having a second memory access node, the first charge input path being a charge path into the second terminal of the first stored charge element and having a substantially definite voltage drop threshold from the second memory access node to the second terminal of the first stored charge element above which conduction occurs and below which significant conduction does not occur; a charge output path having a third memory access node, the first charge output path being a charge path from the second terminal of the first stored charge element and having a substantially definite voltage drop threshold from the second terminal of the first stored charge element to the third memory access node above which conduction occurs and below which significant conduction does not occur; and a latch having an input/output terminal coupled to the second terminal of the stored charge element; wherein at least one of the first, second and third memory access nodes is a bit node, and the charge input path and the charge output path are opposite directions through a bi-directional voltage dropping element having a first terminal coupled to the second terminal of the stored charge device and a second terminal that includes the second and third memory access nodes.

Claim 30

A memory as in claim 25 wherein the latch has a capacitance present at the input/output terminal thereof, the stored charge element being the capacitance of the input/output terminal of the latch.

Claim 31

A memory as in claim 26 wherein the latch comprises: a first inverter having a true input, a complement input, and an output; and a second inverter having a true input, a complement input, and an output, the output of the first inverter being coupled to the true and complement inputs of the second inverter, and the output of the second inverter being coupled to the true and complement inputs of the first inverter; wherein the output of the first inverter is the input/output terminal of the latch.

Claim 32

A memory comprising: a first stored charge element having first and second terminals; a first memory access node coupled to the first terminal of the first stored charge element; a first charge input path having a second memory access node, the first charge input path being a charge path into the second terminal of the first stored charge element and having a substantially definite voltage drop threshold from the second memory access node to the second terminal of the first stored charge element above which conduction occurs and below which significant conduction does not occur; a first charge output path having a third memory access node, the first charge output path being a charge path from the second terminal of the first stored charge element and having a substantially definite voltage drop threshold from the second terminal of the first stored charge element to the third memory access node above which conduction occurs and below which significant conduction does not occur; a second stored charge element having first and second terminals; a fourth memory access node coupled to the first terminal of the second stored charge element; a second charge input path having a fifth memory access node, the second charge input path being a charge path into the second terminal of the second stored charge element and having a substantially definite voltage drop threshold from the fifth memory access node to the second terminal of the second stored charge element above which conduction occurs and below which significant conduction does not occur; and a second charge output path having a sixth memory access node, the second charge output path being a charge path from the second terminal of the second stored charge element and having a substantially definite voltage drop threshold from the second terminal of the second stored charge element to the sixth memory access node above which conduction occurs and below which significant conduction does not occur; a first inverter having a true input, a complement input, and an output; and a second inverter having a true input, a complement input, and an output, the output of the first inverter being coupled to the true and complement inputs of the second inverter, and the output of the second inverter being coupled to the true and complement inputs of the first inverter; wherein: the output of the first inverter is further coupled to the second terminal of the first stored charge element, and the output of the second inverter is further coupled to the second terminal of the second stored charge element; at least one of the first, second and third memory access nodes is a bit node; at least one of the fourth, fifth and sixth memory access nodes is a bit node; the first charge input path and the first charge output path are opposite directions through a first bi-directional voltage dropping element having a first terminal coupled to the second terminal of the first stored charge device and a second terminal that includes the second and third memory access nodes; and the second charge input path and the second charge output path are opposite directions through a second bi-directional voltage dropping element having a first terminal coupled to the second terminal of the second stored charge device and a second terminal that includes the fifth and sixth memory access nodes.

Claim 33

A memory comprising: a first stored charge element having first and second terminals; a first memory access node coupled to the first terminal of the first stored charge element; a first charge input path having a second memory access node, the first charge input path being a charge path into the second terminal of the first stored charge element and having a substantially definite voltage drop threshold from the second memory access node to the second terminal of the first stored charge element above which conduction occurs and below which significant conduction does not occur; a first charge output path having a third memory access node, the first charge output path being a charge path from the second terminal of the first stored charge element and having a substantially definite voltage drop threshold from the second terminal of the first stored charge element to the third memory access node above which conduction occurs and below which significant conduction does not occur; a second stored charge element having first and second terminals; a fourth memory access node coupled to the first terminal of the second stored charge element; a second charge input path having a fifth memory access node, the second charge input path being a charge path into the second terminal of the second stored charge element and having a substantially definite voltage drop threshold from the fifth memory access node to the second terminal of the second stored charge element above which conduction occurs and below which significant conduction does not occur; and a second charge output path having a sixth memory access node, the second charge output path being a charge path from the second terminal of the second stored charge element and having a substantially definite voltage drop threshold from the second terminal of the second stored charge element to the sixth memory access node above which conduction occurs and below which significant conduction does not occur; a first inverter having a true input, a complement input, and an output; and a second inverter having a true input, a complement input, and an output, the output of the first inverter being coupled to the true and complement inputs of the second inverter, and the output of the second inverter being coupled to the true and complement inputs of the first inverter; wherein: the output of the first inverter is further coupled to the second terminal of the first stored charge element, and the output of the second inverter is further coupled to the second terminal of the second stored charge element; at least one of the first, second and third memory access nodes is a bit node; at least one of the fourth, fifth and sixth memory access nodes is a bit node; the first charge input path and the first charge output path are opposite directions through a first bi-directional voltage dropping element having a first terminal coupled to the second terminal of the first stored charge device and a second terminal that includes the second and third memory access nodes; and the second charge input path and the second charge output path are opposite directions through a second bi-directional voltage dropping element having a first terminal coupled to the second terminal of the second stored charge device and a second terminal that includes the fifth and sixth memory access nodes.

Claim 34

A memory comprising: a stored charge element having first and second terminals; a first memory access node coupled to the first terminal of the first stored charge element; a charge input path having a second memory access node, the first charge input path being a charge path into the second terminal of the first stored charge element and having a substantially definite voltage drop threshold from the second memory access node to the second terminal of the first stored charge element above which conduction occurs and below which significant conduction does not occur; a charge output path having a third memory access node, the first charge output path being a charge path from the second terminal of the first stored charge element and having a substantially definite voltage drop threshold from the second terminal of the first stored charge element to the third memory access node above which conduction occurs and below which significant conduction does not occur; and an amplifying valve having a control terminal coupled to the second terminal of the stored charge element, a first current terminal coupled to the first access node, and a second current terminal coupled to a stage output node; wherein the second memory access node is coupled to a precharge line and the third memory access node is coupled to a stage input node.

Claim 35

A memory comprising: a stored charge element having first and second terminals; a first memory access node coupled to the first terminal of the first stored charge element; a charge input path having a second memory access node, the first charge input path being a charge path into the second terminal of the first stored charge element and having a substantially definite voltage drop threshold from the second memory access node to the second terminal of the first stored charge element above which conduction occurs and below which significant conduction does not occur; a charge output path having a third memory access node, the first charge output path being a charge path from the second terminal of the first stored charge element and having a substantially definite voltage drop threshold from the second terminal of the first stored charge element to the third memory access node above which conduction occurs and below which significant conduction does not occur; and an amplifying valve having a control terminal coupled to the second terminal of the stored charge element, a first current terminal coupled to the first access node, and a second current terminal coupled to a stage output node; wherein the second memory access node is coupled to a precharge line and the third memory access node is coupled to a stage input node.

Claim 36

A memory as in claim 29 wherein the amplifying valve is a MOSFET and the first charge storage element is gate capacitance of the MOSFET.

Claim 37

A memory as in claim 1 wherein the first stored charge element, the first charge input path, and the first charge output path form in combination a first memory cell, the first memory access node being a first terminal of the first memory cell and the second and third memory access nodes being in unity as a second terminal of the first memory cell, further comprising a plurality of N-1 additional memory cells, each having: an additional stored charge element having first and second terminals; an additional first memory access node coupled to the first terminal of the additional stored charge element, the additional first memory access node being a first terminal of the additional memory cell; an additional charge input path having an additional second memory access node, the additional charge input path being a charge path into the second terminal of the additional stored charge element and having a substantially definite voltage drop threshold from the additional second memory access node to the second terminal of the additional stored charge element above which conduction occurs and below which significant conduction does not occur; and an additional charge output path having an additional third memory access node, the additional charge output path being a charge path from the second terminal of the additional stored charge element and having a substantially definite voltage drop threshold from the second terminal of the additional stored charge element to the additional third memory access node above which conduction occurs and below which significant conduction does not occur, the second and third additional memory access nodes being in unity as a second terminal of the additional memory cell; wherein: the N memory cells are linked in a closed loop chain such that neighboring memory cells are coupled to one another by one of the respective first and second terminals thereof, the substantially definite voltage drop thresholds of the charge input paths of the N memory cells are substantially equal to a value V I ; the substantially definite voltage drop thresholds of the charge output paths of the N memory cells are substantially equal to a value V O ; and V I and V O are related to a high value of stored voltage V H of the memory cells and a low value of stored voltage V L of the memory cells by the expression V H -V L ≦(V I +V O )(N-2)/N.

Claim 40

A method as in claim 32 wherein the first and second current paths are in opposite directions through a common physical structure.

Claim 41

A method as in claim 33 wherein the first and second substantially definite voltage drop thresholds are obtained from a Zener diode.

Claim 42

A method as in claim 32 wherein the first and second current paths are through different structures that share a common node at a terminal of the stored charge element.

Claim 43

A method as in claim 35 wherein the first and second substantially definite voltage drop thresholds are obtained from respective diodes.

Claim 44

A method as in claim 32 wherein: the first and second voltages are indicative of respective logical states; and the current blocking step comprises blocking current through the first and second current paths during respective intervals following and contiguous with the first and second intervals.

Claim 45

A method as in claim 37 wherein the first voltage is indicative of a logical one and the second voltage is indicative of a logical zero.

Claim 48

A method as in claim 39 wherein the sensed first value of current flow is zero.

Claim 51

A method as in claim 41 wherein the second voltage is indicative of a logical zero and the fourth voltage is indicative of a logical one.

Claim 52

A method as in claim 41 wherein the first and third voltages are equal, further comprising: attempting to flow current during a fifth interval through the first current path to increase voltage across the stored charge element to the first voltage; and sensing current flow during the fifth interval, a sensed first value of current flow indicating a particular one of the plurality of logical states and a sensed second value of current flow indicating another particular one of the plurality of logical states.

Claim 53

A method as in claim 43 wherein the sensed first value of current flow is zero.

Claim 54

A method as in claim 32 wherein: the first interval current flowing step comprises establishing a first voltage differential across a series combination of the first current path and the stored charge element, the first voltage differential being greater than the first substantially definite voltage drop threshold by an amount in effect equal to a first predetermined charge voltage across the stored charge element; and the second interval current flowing step comprises establishing a second voltage differential across a series combination of the second current path and the stored charge element, the second voltage differential being greater than the second substantially definite voltage drop threshold by an amount in effect equal to a second predetermined charge voltage across the stored charge element, the second predetermined charge voltage being less than the first predetermined charge voltage.

Claim 55

A method as in claim 45 wherein the first substantially definite voltage drop threshold is about plus seven tenths of a volt, the first voltage is about 2.85 volts, the first voltage differential is about 3.55 volts, the second substantially definite voltage drop threshold is about five volts, the second voltage is about zero volts, and the second voltage differential is about five volts.

Claim 56

A method as in claim 32 wherein: a voltage V H across the stored charge element is indicative of a first logical state and a voltage V L across the stored charge element is indicative of a second logical state; the substantially definite voltage drop threshold of the first current path is represented by V I and the substantially definite voltage drop threshold of the second current path is represented by V O ; the first interval current flowing step comprises establishing voltages V 1C and V 2C across the first current path and the stored charge element, the voltages V 1C and V 2C being related approximately in accordance with the expression V 2C +V H ≧V I +V 1C ; and the second interval current flowing step comprises establishing voltages V 1D and V 3D across the second current path and the stored charge element, the voltages V 1D and V 3D being related approximately in accordance with the expression V 1D ≧V L +V O +V 3D .

Claim 57

A method as in claim 47 wherein the current blocking step comprises: establishing an idle voltage V 1X and the voltage V 2C across the first current path and the stored charge element, the voltages V 1X and V 2C being related approximately in accordance with the expression V 2C +V L ≦V I +V 1X ; establishing an idle voltage V 1X and the voltage V 3D across the second current path and the stored charge element, the voltages V 1X and V 3D being related approximately in accordance with the expression V 1X ≦V H +V O +V 3D ; establishing an idle voltage V 2X and the voltage V 1C across the first current path and the stored charge element, the voltages V 1C and V 2X being related approximately in accordance with the expression V 2X +V L ≦V I +V 1C establishing an idle voltage V 2X and the voltage V 1D across the first current path and the stored charge element, the voltages V 1D and V 2X being related approximately in accordance with the expression V 2X +V L ≦V I +V 1D ; establishing an idle voltage V 3X and the voltage V 1C across the second current path and the stored charge element, the voltages V 1C and V 3X being related approximately in accordance with the expression V 1C ≦V H +V O +V 3X ; and establishing an idle voltage V 3X and the voltage V 1D across the second current path and the stored charge element, the voltages V 1D and V 3X being related approximately in accordance with the expression V 1D ≦V H +V O +V 3X .

Claim 58

A method as in claim 48 wherein V H exceeds V L by not more than about half of V I +V O .

Claim 61

A method as in claim 50 wherein the amplifying valve is a MOSFET having a gate capacitance, and the stored charge element is the gate capacitance of the MOSFET.

Claim 68

A method as in claim 54 wherein the first conductance characteristic is indicative of a first logical state, the output logical state being the second logical state when the conductance characteristic of the amplifying valve is the first conductance characteristic.

Claim 69

A method as in claim 54 wherein the amplifying valve is a MOSFET having a gate capacitance, and the stored charge element is the gate capacitance of the MOSFET.

Claim 72

A memory as in claim 22 wherein the respective voltage drop thresholds of the charge input path and the charge output path are unequal.

Claim 73

A memory as in claim 58 wherein the charge input path and the charge output path are opposite directions through a bi-directional voltage dropping element having a first terminal coupled to the second terminal of the stored charge device and a second terminal that includes the second and third memory access nodes.

Claim 74

A memory as in claim 59 wherein the bi-directional voltage dropping element is a Zener diode.

Claim 75

A memory as in claim 22 wherein: the control terminal of the amplifying valve has an intrinsic capacitance; and the stored charge element is the intrinsic capacitance of the amplifying valve.

Claim 76

A memory as in claim 60 wherein the amplifying valve is a MOSFET and the charge storage element is gate capacitance of the MOSFET.

Claim 77

A memory as in claim 61 wherein: the amplifying valve is a MOSFET; and the intrinsic capacitance of the amplifying valve is gate capacitance of the MOSFET.

Claim 78

A memory as in claim 63 further comprising a diode connected between the second current terminal of the amplifying valve and the memory read node, the diode having an anode coupled to the memory read node and a cathode coupled to the second current terminal of the amplifying valve.

Claim 79

A memory as in claim 23 wherein conduction through the first and second charge input paths and through the first and second charge output paths occurs with no significant deterioration over time.

Claim 80

A memory as in claim 65 wherein: the first and second stored charge elements are respective integrated circuit capacitors; the first charge input path and the first charge output path are opposite directions through respective integrated circuit diodes; and the second charge input path and the second charge output path are opposite directions through respective integrated circuit diodes.

Claim 81

A memory as in claim 25 wherein the respective voltage drop thresholds of the charge input path and the charge output path are unequal.

Claim 82

A memory as in claim 67 wherein conduction through the charge input path and the charge output path occurs with no significant deterioration over time.

Claim 83

A memory as in claim 68 wherein: the stored charge element is an integrated circuit capacitor; and the charge input path and the charge output path are opposite directions through a Zener diode.

Claim 84

A memory as in claim 28 wherein the respective voltage drop thresholds of the first charge input path and the first charge output path are unequal, and the respective voltage drop thresholds of the second charge input path and the second charge output path are unequal.

Claim 85

A memory as in claim 70 wherein conduction through the first and second charge input paths and through the first and second charge output path occurs with no significant deterioration over time.

Claim 86

A memory as in claim 71 wherein: the first and second stored charge elements are respective integrated circuit capacitors; the first charge input path and the first charge output path are opposite directions through a Zener diode; and the second charge input path and the second charge output path are opposite directions through a Zener diode.

Claim 87

An apparatus as in claim 29 wherein conduction through the charge input path and the charge output path occurs with no significant deterioration over time.

Claim 88

A memory as in claim 73 wherein the charge input path and the charge output path are opposite directions through a bi-directional voltage dropping element.

Claim 89

A memory as in claim 74 wherein the respective voltage drop thresholds of the charge input path and the charge output path through the bi-directional voltage dropping element are unequal.

Claim 90

A memory as in claim 75 wherein the bi-directional voltage dropping element has a first terminal coupled to the second terminal of the stored charge device and a second terminal that includes the second and third memory access nodes.

Claim 91

A memory as in claim 76 wherein the bi-directional voltage dropping element is a Zener diode.

Claim 92

An apparatus as in claim 31 wherein conduction through the charge input path and the charge output path occurs with no significant deterioration over time.

Claim 93

A memory as in claim 31 wherein: the first-mentioned charge input path and the first-mentioned charge output path are opposite directions through respective Zener diodes; and the additional charge input paths and the additional charge output paths are opposite directions through respective Zener diodes.

Claim 94

A method as in claim 39 wherein the first substantially definite voltage drop threshold and the second substantially definite voltage drop threshold are unequal.

Claim 95

A method as in claim 41 wherein the first substantially definite voltage drop threshold and the second substantially definite voltage drop threshold are unequal.

Claim 96

A method as in claim 50 wherein the first substantially definite voltage drop threshold and the second substantially definite voltage drop threshold are unequal.

Claim 97

A method as in claim 52 wherein the first substantially definite voltage drop threshold and the second substantially definite voltage drop threshold are unequal.

Claim 98

A method as in claim 53 wherein the first substantially definite voltage drop threshold and the second substantially definite voltage drop threshold are unequal.

Claim 99

A method as in claim 54 wherein the first substantially definite voltage drop threshold and the second substantially definite voltage drop threshold are unequal.

Claim 100

A method as in claim 57 wherein the first substantially definite voltage drop threshold and the second substantially definite voltage drop threshold are unequal.