US5508955A
Expired / Lapsed
US
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Electronically erasable-programmable memory cell having buried bit line
Assignee: Winbond Electronics Corp
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Filing: 1993-05-20
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Granted: 1996-04-16
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Expires: 2013-05-20
Abstract
Abstract A memory cell (510) suitable for an array of memory cells (100) has a source that is part of a buried bit line and a drain that is part of an adjacent buried bit line. The memory cell also includes a split gate arrangement (580) in which the gate is integral with the word line (120), with a part of the gate being the control gate of an EEPROM transistor which erases and programs on the principle of Fowler-Nordheim tunneling (560, 570), and another part of the gate being the control gate of a series select transistor. The memory cell is erased by placing a voltage on the word line which is positive relative to the bit line and the substrate and of sufficient magnitude to cause tunneling. The memory cell is programmed by placing a negative voltage on the word line and a voltage corresponding to the logical value on the bit line. The bit line voltage is sufficient to cause tunneling for one logical value, and insufficient to cause tunneling for the other logical value. The memory cell is read by placing a sense voltage across the bit lines forming its source and drain, and a read voltage on the control gate. Other bit lines are left floating.
Inventors
- 👤 Jan Zimmer
- 👤 Nagesh Challa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 22:25
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683; G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0491; H10B; H10B69/00
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
238 words
A memory cell that is electrically erasable and programmable, comprising: a semiconductor body of a first conductivity type having a generally planar surface region; a first electrically conductive line of a second conductivity type extending into the semiconductor body from the generally planar surface region, the first line including a data carrying capability; a second electrically conductive line of the second conductivity type extending into the semiconductor body from the generally planar surface region and spaced apart from the first line; a first section comprising a drain formed at least in part by the first line, a first channel region disposed adjacent the drain in the semiconductor body, a floating gate overlapping the first channel region and further overlapping at least a portion of the drain and insulated therefrom by a dielectric for supporting Fowler-Nordheim tunneling, and a first control gate overlapping at least a portion of the floating gate over the first channel region, the first channel region being within control of the floating gate and the first control gate; and a second section comprising a source formed at least in part by the second line, a second channel region disposed adjacent the source in the semiconductor body, and a second control gate, overlapping the second channel region, the second channel region being within control of the second control gate, the first and second control gates being integral, and the first and second channel regions being integral.
Claim 2
Dependent Claim
238 words
A memory cell that is electrically erasable and programmable, comprising: a semiconductor body of a first conductivity type having a generally planar surface region; a first electrically conductive line of a second conductivity type extending into the semiconductor body from the generally planar surface region, the first line including a data carrying capability; a second electrically conductive line of the second conductivity type extending into the semiconductor body from the generally planar surface region and spaced apart from the first line; a first section comprising a drain formed at least in part by the first line, a first channel region disposed adjacent the drain in the semiconductor body, a floating gate overlapping the first channel region and further overlapping at least a portion of the drain and insulated therefrom by a dielectric for supporting Fowler-Nordheim tunneling, and a first control gate overlapping at least a portion of the floating gate over the first channel region, the first channel region being within control of the floating gate and the first control gate; and a second section comprising a source formed at least in part by the second line, a second channel region disposed adjacent the source in the semiconductor body, and a second control gate, overlapping the second channel region, the second channel region being within control of the second control gate, the first and second control gates being integral, and the first and second channel regions being integral.
Claim 3
Dependent Claim
22 words
A memory cell as in claim 1 wherein the substrate is a p-type region and the first line is an n-type region.
Claim 4
Dependent Claim
17 words
A memory cell as in claim 2 wherein the first line is a heavily doped n-type region.
Claim 5
Dependent Claim
16 words
A memory cell as in claim 1 wherein the second line includes a data carrying capability.
Claim 6
Dependent Claim
29 words
A memory cell as in claim 4 wherein the substrate is a p-type region, the first line is an n-type region, and the second line is an n-type region.
Claim 7
Dependent Claim
18 words
A memory cell as in claim 5 wherein the first and second lines are heavily doped n-type regions.
Claim 8
Dependent Claim
31 words
A memory cell as in claim 1 wherein the first and second control gates are part of a word line, and wherein the first line is part of a bit line.
Claim 9
Dependent Claim
210 words
A memory cell that is electrically erasable and programmable, comprising: a p-type semiconductor body; a first n-type bit line extending into the semiconductor body from a first surface strip of the semiconductor body; a second n-type bit line extending into the semiconductor body from a second surface strip of the semiconductor body, the second bit line being parallel to the first bit line; a control gate comprising an electrically conductive polysilicon strip disposed over the semiconductor body and transverse to the first and second bit line for controlling a channel region disposed in the semiconductor body under a third surface strip and between the first and second bit lines, the first, second and third surface strips being coplanar and a portion of the first bit line being adjacent the channel region for functioning as a drain, and a portion of the second bit line being adjacent the channel region for functioning as a source; and a floating gate comprising a polysilicon element disposed between a portion of the polysilicon strip and a portion of the semiconductor body comprising a portion of the drain and a portion of the channel region adjacent the drain, the floating gate polysilicon element being separated from the drain by a dielectric for supporting Fowler-Nordheim tunneling.
Claim 10
Dependent Claim
210 words
A memory cell that is electrically erasable and programmable, comprising: a p-type semiconductor body; a first n-type bit line extending into the semiconductor body from a first surface strip of the semiconductor body; a second n-type bit line extending into the semiconductor body from a second surface strip of the semiconductor body, the second bit line being parallel to the first bit line; a control gate comprising an electrically conductive polysilicon strip disposed over the semiconductor body and transverse to the first and second bit line for controlling a channel region disposed in the semiconductor body under a third surface strip and between the first and second bit lines, the first, second and third surface strips being coplanar and a portion of the first bit line being adjacent the channel region for functioning as a drain, and a portion of the second bit line being adjacent the channel region for functioning as a source; and a floating gate comprising a polysilicon element disposed between a portion of the polysilicon strip and a portion of the semiconductor body comprising a portion of the drain and a portion of the channel region adjacent the drain, the floating gate polysilicon element being separated from the drain by a dielectric for supporting Fowler-Nordheim tunneling.
Claim 11
Dependent Claim
22 words
A memory element as in claim 8 wherein the polysilicon element is separated from the semiconductor body portion by a tunnel dielectric.
Claim 12
Dependent Claim
163 words
An electrically erasable and programmable memory array comprising: a semiconductor body having a generally planar major surface; a plurality of buried data carrying lines extending into the semiconductor body from the major surface thereof; a plurality of word lines; a plurality of memory cells, each of the memory cells being associated with one of the word lines and one of the data carrying lines and comprising a select transistor coupled to an electrically erasable programmable read-only memory ("EEPROM") transistor, the EEPROM transistor having a control gate and a floating gate and further having a drain insulated from the floating gate by a tunnel dielectric and coupled to the associated one of the data carrying lines, the select transistor having a control gate and further having a source coupled to one of the data carrying lines adjacent the associated data carrying line, the control gates of the select transistor and the EEPROM transistor being commonly coupled to the associated one of the word lines.
Claim 13
Dependent Claim
163 words
An electrically erasable and programmable memory array comprising: a semiconductor body having a generally planar major surface; a plurality of buried data carrying lines extending into the semiconductor body from the major surface thereof; a plurality of word lines; a plurality of memory cells, each of the memory cells being associated with one of the word lines and one of the data carrying lines and comprising a select transistor coupled to an electrically erasable programmable read-only memory ("EEPROM") transistor, the EEPROM transistor having a control gate and a floating gate and further having a drain insulated from the floating gate by a tunnel dielectric and coupled to the associated one of the data carrying lines, the select transistor having a control gate and further having a source coupled to one of the data carrying lines adjacent the associated data carrying line, the control gates of the select transistor and the EEPROM transistor being commonly coupled to the associated one of the word lines.
Claim 14
Dependent Claim
206 words
An electrically erasable and programmable memory array comprising: a semiconductor body having a generally planar major surface; a plurality of substantially parallel data carrying lines extending into the semiconductor body from the major surface thereof; a plurality of substantially parallel word lines disposed over the semiconductor body, the word lines being transverse to the data carrying lines; and a plurality of memory cells, each of the memory cells being associated with one of the word lines and one of the data carrying lines and comprising a select transistor having a control gate for controlling a first channel, integrated with an electrically erasable programmable read-only memory ("EEPROM") transistor having a control gate for controlling a second channel and a floating gate, the EEPROM transistor further having a drain comprising a pan of the associated one of the data carrying lines and insulated from the floating gate by a tunnel dielectric, the select transistor having a source comprising a part of one of the data carrying lines adjacent the associated data carrying line, the control gates of the select transistor and the EEPROM transistor being integral with the associated word line, and the first and second channels of the select transistor and the EEPROM transistor respectively being integral.
Claim 15
Dependent Claim
206 words
An electrically erasable and programmable memory array comprising: a semiconductor body having a generally planar major surface; a plurality of substantially parallel data carrying lines extending into the semiconductor body from the major surface thereof; a plurality of substantially parallel word lines disposed over the semiconductor body, the word lines being transverse to the data carrying lines; and a plurality of memory cells, each of the memory cells being associated with one of the word lines and one of the data carrying lines and comprising a select transistor having a control gate for controlling a first channel, integrated with an electrically erasable programmable read-only memory ("EEPROM") transistor having a control gate for controlling a second channel and a floating gate, the EEPROM transistor further having a drain comprising a pan of the associated one of the data carrying lines and insulated from the floating gate by a tunnel dielectric, the select transistor having a source comprising a part of one of the data carrying lines adjacent the associated data carrying line, the control gates of the select transistor and the EEPROM transistor being integral with the associated word line, and the first and second channels of the select transistor and the EEPROM transistor respectively being integral.
Claim 16
Dependent Claim
123 words
An electrically erasable and programmable memory cell disposed in a generally planar surface region of a semiconductor substrate, comprising: a first doped region extending into the substrate from the surface region, the first doped region providing a bit line connectable to other cells in a column; a second doped region extending into the substrate from the surface region and separated from the first doped region by a channel region; a floating gate disposed over a portion of the channel region and insulated therefrom by a dielectrics and further disposed over a portion of the first doped region and insulated therefrom by a tunnel dielectric; a control gate disposed over the floating gate and over the channel region, and insulated therefrom by a dielectric.
Claim 17
Dependent Claim
123 words
An electrically erasable and programmable memory cell disposed in a generally planar surface region of a semiconductor substrate, comprising: a first doped region extending into the substrate from the surface region, the first doped region providing a bit line connectable to other cells in a column; a second doped region extending into the substrate from the surface region and separated from the first doped region by a channel region; a floating gate disposed over a portion of the channel region and insulated therefrom by a dielectrics and further disposed over a portion of the first doped region and insulated therefrom by a tunnel dielectric; a control gate disposed over the floating gate and over the channel region, and insulated therefrom by a dielectric.
Claim 18
Dependent Claim
21 words
A memory cell as in claim 12 wherein the first and second doped regions are n-type and the substrate is p-type.
Claim 19
Dependent Claim
24 words
A memory cell as in claim 13 wherein: the floating gate and the word line comprise polysilicon; and the tunnel dielectric comprises silicon dioxide.
Claim 20
Dependent Claim
173 words
An array of electrically erasable and programmable memory cells disposed in a region of a semiconductor substrate, comprising: a first doped region extending into the substrate from a first generally planar strip-like surface region of the substrate, the first doped region providing a bit line; and a second doped region extending into the substrate from a second generally planar strip-like surface region of the substrate, the second doped region being parallel to the first doped region; wherein each of the memory cells comprises: a channel region disposed between the first doped region and the second doped region and extending from a third generally planar surface region of the substrate, the first, second and third surface regions being coplanar; a floating gate disposed over a portion of the channel region and insulated therefrom by a dielectric, and further disposed over a portion of the first dope region and insulated therefrom by a tunnel dielectric; and a control gate disposed over the floating gate and over the channel region, and insulated therefrom by a dielectric.
Claim 21
Dependent Claim
173 words
An array of electrically erasable and programmable memory cells disposed in a region of a semiconductor substrate, comprising: a first doped region extending into the substrate from a first generally planar strip-like surface region of the substrate, the first doped region providing a bit line; and a second doped region extending into the substrate from a second generally planar strip-like surface region of the substrate, the second doped region being parallel to the first doped region; wherein each of the memory cells comprises: a channel region disposed between the first doped region and the second doped region and extending from a third generally planar surface region of the substrate, the first, second and third surface regions being coplanar; a floating gate disposed over a portion of the channel region and insulated therefrom by a dielectric, and further disposed over a portion of the first dope region and insulated therefrom by a tunnel dielectric; and a control gate disposed over the floating gate and over the channel region, and insulated therefrom by a dielectric.
Claim 22
Dependent Claim
21 words
A memory cell as in claim 15 wherein the first and second doped regions are n-type and the substrate is p-type.
Claim 23
Dependent Claim
24 words
A memory cell as in claim 15 wherein: the floating gate and the word line comprise polysilicon; and the tunnel dielectric comprises silicon dioxide.
Claim 24
Dependent Claim
31 words
A memory cell as in claim 7 wherein the first and second channel regions comprise a dopant having a substantially uniform distribution in a direction parallel to the substantially planar surface.
Claim 25
Dependent Claim
18 words
A memory cell as in claim 8 wherein the control gate is a region of a word line.
Claim 26
Dependent Claim
28 words
A memory cell as in claim 19 wherein the channel region comprises a dopant having a substantially uniform distribution in a direction parallel to the third surface strip.
Claim 27
Dependent Claim
29 words
A memory cell as in claim 10 wherein the control gates of the select transistor and the EEPROM transistor comprise portions of the associated one of the word lines.
Claim 28
Dependent Claim
35 words
A memory cell as in claim 21 wherein the select and EEPROM transistors comprise an integrated channel with a dopant having a substantially uniform distribution in a direction parallel to the generally planar major surface.
Claim 29
Dependent Claim
26 words
A memory cell as in claim 11 wherein the control gates of the select transistor and the EEPROM transistor comprise portions of the associated word line.
Claim 30
Dependent Claim
31 words
A memory cell as in claim 23 wherein the first and second channels comprise a dopant having a substantially uniform distribution in a direction parallel to the generally planar major surface.
Claim 31
Dependent Claim
18 words
A memory cell as in claim 12 wherein the control gate comprises a portion of a word line.
Claim 32
Dependent Claim
29 words
A memory cell as in claim 25 wherein the channel region comprises a dopant having a substantially uniform distribution in a direction parallel to the generally planar surface region.
Claim 33
Dependent Claim
24 words
A memory cell as in claim 25 wherein the control gate of each of the memory cells comprises a portion of a word line.
Claim 34
Dependent Claim
28 words
A memory cell as in claim 27 wherein the channel region comprises a dopant having a substantially uniform distribution in a direction parallel to the third surface region.
References Cited (Backward Citations)
US4328565A
Cited
US4622656A
Cited
US4639893A
Cited
US4949140A
Cited
US5047814A
Cited
US5101250A
Cited
US4996668A
Cited
US5262987A
Cited
US5041886A
Cited
US5241499A
Cited
US5115288A
Cited
US5130769A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-16 | 1999-10-16 | 2000-04-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-16 | 2003-10-16 | 2004-04-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-16 | 2007-10-16 | 2008-04-16 | $7700.00 | Window Closed / Lapsed |