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US5267192A
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Semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1991-08-30
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Granted: 1993-11-30
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Expires: 2011-08-30
Abstract
Abstract A semiconductor memory device having a plurality of memory cells, each memory cell having two nodes, an electric potential of each node designates a stored data, comprises: a word line; a pair of bit lines; a pair of field effect transistors (FETs) connected between the word line and the nodes; a pair of diodes connected between the bit lines and the nodes; a pair of load means connected between the nodes and a first potential; and an inverter connected to the word line for driving the FETs, wherein the electrical potential of the nodes are read out by the change of the potential of the word line controlled by the inverter.
Inventors
- 👤 Kazutaka Nogami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 20:53
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
183 words
A semiconductor memory device having a plurality of memory cells, each of said memory cells having two nodes, wherein an electric potential of each of said nodes designates a stored data, comprising: a word line; a pair of bit lines; a pair of field effect transistors (FETs) connected between the word line and the nodes; a pair of diodes connected between the bit lines and the nodes; a pair of load means connected between the nodes and a first potential; and driving means connected to the word line for driving the FETs by gradually reducing the electric potential of the word line to a ground level; wherein the difference in electric potential between the nodes and the word line is set to a value which is smaller than the electric potential of the threshold voltages of the FETs, the drivability of the driving means is set to a value which is smaller than that of the FETs, and wherein the electric potentials of the nodes are set by the change in potential of the word line under the control of the driving means.
Claim 2
Dependent Claim
183 words
A semiconductor memory device having a plurality of memory cells, each of said memory cells having two nodes, wherein an electric potential of each of said nodes designates a stored data, comprising: a word line; a pair of bit lines; a pair of field effect transistors (FETs) connected between the word line and the nodes; a pair of diodes connected between the bit lines and the nodes; a pair of load means connected between the nodes and a first potential; and driving means connected to the word line for driving the FETs by gradually reducing the electric potential of the word line to a ground level; wherein the difference in electric potential between the nodes and the word line is set to a value which is smaller than the electric potential of the threshold voltages of the FETs, the drivability of the driving means is set to a value which is smaller than that of the FETs, and wherein the electric potentials of the nodes are set by the change in potential of the word line under the control of the driving means.
Claim 3
Dependent Claim
15 words
A semiconductor memory device according to claim 1, wherein the driving means comprises an inverter.
Claim 4
Dependent Claim
72 words
A semiconductor memory device according to claim 1, wherein the FETs are made up of n-channel metal oxide semiconductors, the gate of one FET is connected to one node and the gate of the other FET to the other node, the drains of the FETs are connected to the word line, the anodes of the diodes are connected to the bit lines, and the cathods of which are connected to the nodes.
Claim 5
Dependent Claim
15 words
A semiconductor memory device according to claim 2, wherein the load means comprises a resistance.
Claim 6
Dependent Claim
17 words
A semiconductor memory device according to claim 2, wherein the load means comprises a p-channel MOS FET.
Claim 7
Dependent Claim
74 words
A semiconductor memory device according to claim 1, wherein the load means is made up of p-channel metal oxide semiconductor FET, the gate of one FET is connected to one node and the gate of the other FET to the other node, the drains of the FETs are connected to the word line, the cathods of the diodes are connected to the bit lines, and the anodes of which are connected to the nodes.
Claim 8
Dependent Claim
15 words
A semiconductor memory device according to claim 6, wherein the driving means comprises an inverter.
Claim 9
Dependent Claim
15 words
A semiconductor memory device according to claim 6, wherein the load means comprises a resistance.
Claim 10
Dependent Claim
17 words
A semiconductor memory device according to claim 6, wherein the load means comprises a p-channel MOS FET.
Claim 11
Dependent Claim
29 words
A semiconductor memory device according to claim 1, wherein an output potential of the first potential changes at the same phases as the potential provided to the word line.
References Cited (Backward Citations)
US4023148A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-11-29 | 1997-05-31 | 1997-11-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-11-29 | 2001-05-31 | 2001-11-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-11-29 | 2005-05-31 | 2005-11-30 | $7700.00 | Window Closed / Lapsed |