Three terminal tunnel device

Claim 2

A field effect transistor exhibiting a current-voltage characteristic of the negative differential resistance type, said field effect transistor, comprising: an isolation region; an intermediate region made of a non-degenerated semiconductor and provided on said isolation region; an insulation layer formed on said intermediate region so that said insulation layer and said isolation region sandwich said intermediate region; a source region made of a degenerated semiconductor of a first conductivity type, said source region being provided on said isolation region and being in contact with a first end of said intermediate region; a drain region made of a degenerated semiconductor of a second conductivity type, said drain region being provided on said isolation region and being in contact with a second end of said intermediate region; and a control electrode provided on said insulation layer for applying an electric field to said intermediate region; wherein said intermediate region has a thickness of approximately 200 angstroms, which allows at least an upper part of said intermediate region to change from said non-degenerated semiconductor into a degenerated semiconductor by said electric field, so as to substantially suppress a diffusion current flowing between said source and drain regions to thereby prevent any substantial increase of valley current involved in said current-voltage characteristic; and wherein said isolation region comprises an insulator selected from the group consisting of SiO 2 , SiN4, SiON, Al 2 O 3 , TiO 2 , PbZrTiO 3 , and CaF.

Claim 3

The field effect transistor as claimed in claim 1, wherein said source and drain regions are respectively provided with ohmic contacts.

Claim 4

The field effect transistor as claimed in claim 1, wherein said source, drain and intermediate regions are made of the same semiconductor to form a homojunction.

Claim 5

The field effect transistor as claimed in claim 1, wherein said source, drain and intermediate regions are made of different semiconductors to form a heterojunction.

Claim 6

A field effect transistor exhibiting a current-voltage characteristic of the negative differential resistance type, said field effect transistor, comprising: an isolation region; an intermediate region made of a non-degenerated semiconductor and provided on said isolation region; an insulation layer formed on said intermediate region so that said insulation layer and said isolation region sandwich said intermediate region; a source region made of a degenerated semiconductor of a first conductivity type, said source region being provided on said isolation region and being in contact with a first end of said intermediate region; a drain region made of a degenerated semiconductor of a second conductivity type, said drain region being provided on said isolation region and being in contact with a second end of said intermediate region; and a control electrode provided on said insulation layer for applying an electric field to said intermediate region; wherein said intermediate region has a thickness of approximately 200 angstroms, which allows at least an upper part of said intermediate region to change from said non-degenerated semiconductor into a degenerated semiconductor by said electric field, so as to substantially suppress a diffusion current flowing between said source and drain regions to thereby prevent any substantial increase of valley current involved in said current-voltage characteristic; and wherein said isolation region comprises a semiconductor material having a significantly wider band gap than that of said source, drain and intermediate regions.

Claim 7

A field effect transistor exhibiting a current-voltage characteristic of the negative differential resistance type, said field effect transistor, comprising: an isolation region; an intermediate region made of a non-degenerated semiconductor and provided on said isolation region; an insulation layer formed on said intermediate region so that said insulation layer and said isolation region sandwich said intermediate region; a source region made of a degenerated semiconductor of a first conductivity type, said source region being provided on said isolation region and being in contact with a first end of said intermediate region; a drain region made of a degenerated semiconductor of a second conductivity type, said drain region being provided on said isolation region and being in contact with a second end of said intermediate region; and a control electrode provided on said insulation layer for applying an electric field to said intermediate region; wherein said intermediate region has a thickness of approximately 200 angstroms, which allows at least an upper part of said intermediate region to change from said non-degenerated semiconductor into a degenerated semiconductor by said electric field, so as to substantially suppress a diffusion current flowing between said source and drain regions to thereby prevent any substantial increase of valley current involved in said current-voltage characteristic; and wherein said isolation region comprises a semiconductor material having a significantly wider band gap than that of said source, drain and intermediate regions.

Claim 8

The field effect transistor as claimed in claim 1, wherein said non-degenerated semiconductor in said intermediate region is an intrinsic semiconductor.

Claim 9

The field effect transistor as claimed in claim 1, wherein said non-degenerated semiconductor in said intermediate region is doped by a dopant of the first conductivity type.

Claim 10

The field effect transistor as claimed in claim 1, wherein said non-degenerated semiconductor in said intermediate region is doped by a dopant of the second conductivity type.

Claim 11

A field effect transistor exhibiting a current-voltage characteristic of the negative differential resistance type, said field effect transistor, comprising: an isolation region; an intermediate region made of a degenerated semiconductor and provided on said isolation region; an insulation layer formed on said intermediate region so that said insulation layer and said isolation region sandwich said intermediate region; a source region made of a degenerated semiconductor of a first conductivity type, said source region being provided on said isolation region and being in contact with a first end of said intermediate region; a drain region made of a degenerated semiconductor of a second conductivity type, said drain region being provided on said isolation region and being in contact with a second end of said intermediate region; and a control electrode provided on said insulation layer for applying an electric field to said intermediate region; wherein said intermediate region has a thickness of approximately 200 angstroms, which allows at least an upper part of said intermediate region to change from said degenerated semiconductor into a non-degenerated semiconductor by said electric field, so as to substantially suppress a diffusion current flowing between said source and drain regions to thereby prevent any substantial increase of valley current involved in said current-voltage characteristic; and wherein said isolation region comprises an insulator selected from the group consisting of SiO 2 , SiN 4 , SiON, Al 2 O 3 , TiO 2 , PbZrTiO 3 , and CaF.

Claim 12

A field effect transistor exhibiting a current-voltage characteristic of the negative differential resistance type, said field effect transistor, comprising: an isolation region; an intermediate region made of a degenerated semiconductor and provided on said isolation region; an insulation layer formed on said intermediate region so that said insulation layer and said isolation region sandwich said intermediate region; a source region made of a degenerated semiconductor of a first conductivity type, said source region being provided on said isolation region and being in contact with a first end of said intermediate region; a drain region made of a degenerated semiconductor of a second conductivity type, said drain region being provided on said isolation region and being in contact with a second end of said intermediate region; and a control electrode provided on said insulation layer for applying an electric field to said intermediate region; wherein said intermediate region has a thickness of approximately 200 angstroms, which allows at least an upper part of said intermediate region to change from said degenerated semiconductor into a non-degenerated semiconductor by said electric field, so as to substantially suppress a diffusion current flowing between said source and drain regions to thereby prevent any substantial increase of valley current involved in said current-voltage characteristic; and wherein said isolation region comprises an insulator selected from the group consisting of SiO 2 , SiN 4 , SiON, Al 2 O 3 , TiO 2 , PbZrTiO 3 , and CaF.

Claim 13

The field effect transistor as claimed in claim 9, wherein said source and drain regions are respectively provided with ohmic contacts.

Claim 14

The field effect transistor as claimed in claim 9, wherein said source, drain and intermediate regions are made of the same semiconductor to form a homojunction.

Claim 15

The field effect transistor as claimed in claim 9, wherein said source, drain and intermediate regions are made of different semiconductors to form a heterojunction.

Claim 16

The field effect transistor as claimed in claim 9, wherein said non-degenerated semiconductor in said intermediate region is doped by a dopant of the first conductivity type.

Claim 17

The field effect transistor as claimed in claim 9, wherein said non-degenerated semiconductor in said intermediate region is doped by a dopant of the second conductivity type.

Claim 18

The field effect transistor as claimed in claim 5, wherein said source and drain regions are respectively provided with ohmic contacts.

Claim 19

The field effect transistor as claimed in claim 5, wherein said source, drain and intermediate regions are made of the same semiconductor to form a homojunction.

Claim 20

The field effect transistor as claimed in claim 5, wherein said source, drain and intermediate regions are made of different semiconductors to form a heterojunction.

Claim 21

The field effect transistor as claimed in claim 5, wherein said non-degenerated semiconductor in said intermediate region is an intrinsic semiconductor.

Claim 22

The field effect transistor as claimed in claim 5, wherein said non-degenerated semiconductor in said intermediate region is doped by a dopant of the first conductivity type.

Claim 23

The field effect transistor as claimed in claim 5, wherein said non-degenerated semiconductor in said intermediate region is doped by a dopant of the second conductivity type.

Claim 24

A field effect transistor exhibiting a current-voltage characteristic of the negative differential resistance type, said field effect transistor, comprising: an isolation region; an intermediate region made of a degenerated semiconductor and provided on said isolation region; an insulation layer formed on said intermediate region so that said insulation layer and said isolation region sandwich said intermediate region; a source region made of a degenerated semiconductor of a first conductivity type, said source region being provided on said isolation region and being in contact with a first end of said intermediate region; a drain region made of a degenerated semiconductor of a second conductivity type, said drain region being provided on said isolation region and being in contact with a second end of said intermediate region; and a control electrode provided on said insulation layer for applying an electric field to said intermediate region; wherein said intermediate region has a thickness of approximately 200 angstroms, which allows at least an upper part of said intermediate region to change from said degenerated semiconductor into a non-degenerated semiconductor by said electric field, so as to substantially suppress a diffusion current flowing between said source and drain regions to thereby prevent any substantial increase of valley current involved in said current-voltage characteristic; and wherein said isolation region comprises a semiconductor material having a significantly wider band gap than that of said source, drain and intermediate regions.

Claim 25

A field effect transistor exhibiting a current-voltage characteristic of the negative differential resistance type, said field effect transistor, comprising: an isolation region; an intermediate region made of a degenerated semiconductor and provided on said isolation region; an insulation layer formed on said intermediate region so that said insulation layer and said isolation region sandwich said intermediate region; a source region made of a degenerated semiconductor of a first conductivity type, said source region being provided on said isolation region and being in contact with a first end of said intermediate region; a drain region made of a degenerated semiconductor of a second conductivity type, said drain region being provided on said isolation region and being in contact with a second end of said intermediate region; and a control electrode provided on said insulation layer for applying an electric field to said intermediate region; wherein said intermediate region has a thickness of approximately 200 angstroms, which allows at least an upper part of said intermediate region to change from said degenerated semiconductor into a non-degenerated semiconductor by said electric field, so as to substantially suppress a diffusion current flowing between said source and drain regions to thereby prevent any substantial increase of valley current involved in said current-voltage characteristic; and wherein said isolation region comprises a semiconductor material having a significantly wider band gap than that of said source, drain and intermediate regions.

Claim 26

The field effect transistor as claimed in claim 21, wherein said source and drain regions are respectively provided with ohmic contacts.

Claim 27

The field effect transistor as claimed in claim 21, wherein said source, drain and intermediate regions are made of the same semiconductor to form a homojunction.

Claim 28

The field effect transistor as claimed in claim 21, wherein said source, drain and intermediate regions are made of different semiconductors to form a heterojunction.

Claim 29

The field effect transistor as claimed in claim 21, wherein said non-degenerated semiconductor in said intermediate region is doped by a dopant of the first conductivity type.

Claim 30

The field effect transistor as claimed in claim 21, wherein said non-degenerated semiconductor in said intermediate region is doped by a dopant of the second conductivity type.