Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
113 words
A processor comprising: means for outputting, to a memory device during a first memory operation, address segment signals alternatively representing one of at least two address segments which, when concatenated together, represent a full address for addressing said memory device; means for outputting, to said memory device during said first memory operation, a first mode control signal indicating which one of said at least two address segments, said address segment signals represent; and means for outputting, to said memory device during a second memory operation, a second mode control signal indicating that a previously output address segment shall be modified without outputting said address segment signals from said address segment signal output means.
Claim 2
Dependent Claim
113 words
A processor comprising: means for outputting, to a memory device during a first memory operation, address segment signals alternatively representing one of at least two address segments which, when concatenated together, represent a full address for addressing said memory device; means for outputting, to said memory device during said first memory operation, a first mode control signal indicating which one of said at least two address segments, said address segment signals represent; and means for outputting, to said memory device during a second memory operation, a second mode control signal indicating that a previously output address segment shall be modified without outputting said address segment signals from said address segment signal output means.
Claim 3
Dependent Claim
25 words
The processor of claim 1, wherein the second mode control signal indicates that a previously output address segment shall be incremented by a predetermined amount.
Claim 4
Dependent Claim
66 words
A processor comprising: means for outputting, to a memory device, signals causing a read operation of said memory device during a first memory operation; and means for outputting, to said memory device during a second memory operation, a mode control signal indicating that said memory device is to use, as at least part of a full address, data that was read during said first memory operation.
Claim 5
Dependent Claim
66 words
A processor comprising: means for outputting, to a memory device, signals causing a read operation of said memory device during a first memory operation; and means for outputting, to said memory device during a second memory operation, a mode control signal indicating that said memory device is to use, as at least part of a full address, data that was read during said first memory operation.
Claim 6
Dependent Claim
72 words
A processor comprising: means for outputting, to a memory device, signals causing a read operation of said memory device during first and second memory operations; and means for outputting, to said memory device during a third memory operation, a mode control signal indicating that said memory device is to use, as at least part of a full address, a concatenation of data that was read during said first and second memory operations.
Claim 7
Dependent Claim
72 words
A processor comprising: means for outputting, to a memory device, signals causing a read operation of said memory device during first and second memory operations; and means for outputting, to said memory device during a third memory operation, a mode control signal indicating that said memory device is to use, as at least part of a full address, a concatenation of data that was read during said first and second memory operations.
Claim 8
Dependent Claim
93 words
A processor comprising: means for outputting, to a first memory device during a first memory operation, address segment signals alternatively representing one of at least two address segments which, when concatenated together, represent a full address for addressing said first memory device; means for outputting, to said first memory device during said first memory operation, a first mode control signal indicating which one of said at least two address segments, said address segment signals represent; and means for outputting, to a second memory device, a full address for addressing said second memory device.
Claim 9
Dependent Claim
93 words
A processor comprising: means for outputting, to a first memory device during a first memory operation, address segment signals alternatively representing one of at least two address segments which, when concatenated together, represent a full address for addressing said first memory device; means for outputting, to said first memory device during said first memory operation, a first mode control signal indicating which one of said at least two address segments, said address segment signals represent; and means for outputting, to a second memory device, a full address for addressing said second memory device.
Claim 10
Dependent Claim
19 words
The processor of claim 5, wherein the first memory device is for storing instructions for execution by said processor.