System for single cycle transfer of unmodified data to a next sequentially higher address in a semiconductor memory

Claim 1

An electronic processor in which data is cyclically processed, comprising: a semiconductor memory arranged and adapted to be read from and written to, including an array of memory cells arranged in rows and columns identifying memory locations of said semiconductor memory, each of said memory locations having a unique address, said array divided into a first half containing memory locations with even numbered addresses and a second half containing memory locations with odd numbered addresses, signal generating means electrically connected to said semiconductor memory for generating electrical shift signals to increment the addresses of said memory locations through a sequence of consecutively higher numbered addresses, selecting means for selecting an address designating a memory location from among the memory locations from which data is to be read, access means responsive to the selection of an address for reading data from the memory location designated by said selected address in one of said first and second halves during a predetermined instruction processing cycle of said electronic processor, and shift means responsive to an electrical shift signal generated by said signal generating means in response to the reading of data by said access means from said designated memory location for automatically writing data read from said designated memory location into the memory location in the other of said first and second halves of said array designated by the next sequentially higher address relative to said selected address during the same said predetermined instruction processing cycle.

Claim 6

A method for transferring data between address locations of a semiconductor memory, comprising: partitioning said memory into first and second halves one of which contains all odd numbered address locations and the other of which contains all even numbered address locations of the memory, reading data from a selected address location in one of said halves during an instruction cycle of operation, and incrementing the addresses of said memory such that the same data which was read from the selected address location is written into the next sequentially higher address location of said memory in the other of said halves during a single instruction cycle of operation in which both reading from and writing into the respective halves of said memory takes place.

Claim 7

A method for transferring data between address locations of a semiconductor memory, comprising: partitioning said memory into first and second halves one of which contains all odd numbered address locations and the other of which contains all even numbered address locations of the memory, reading data from a selected address location in one of said halves during an instruction cycle of operation, and incrementing the addresses of said memory such that the same data which was read from the selected address location is written into the next sequentially higher address location of said memory in the other of said halves during a single instruction cycle of operation in which both reading from and writing into the respective halves of said memory takes place.