US4479178A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Quadruply time-multiplex information bus
Assignee: Texas Instruments Inc
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Filing: 1981-07-02
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Granted: 1984-10-23
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Expires: 2001-07-02
Abstract
Abstract A quadruply time-multiplexed bus for digital processor systems. The quadruply time-multiplexed information bus is interfaced to a processor and an external memory to transfer addresses, data and program instructions between the processor and the external memory. The interface at the external memory includes the capability to store the addresses of extended bus or instructions being accessed. These stored addresses may be modified from the processor by the processor transmitting new addresses over the information bus or by having the processor activate selected control signals in the information bus interface which causes the stored address to be modified in response to the control signals. This feature is useful to read a new instruction from external memory without the requirement of a new transmission of program instruction address every time a new instruction is fetched by the processor.
Inventors
- 👤 John Schabowski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 12:23
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4239; G06F12/00; G06F12/02; G06F12/0215
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
191 words
A digital processor system comprising: memory means for storing of information; processor means for entering and extracting information from the memory means under the control of a predetermined program sequence; interface means coupled between said processor means and memory means for providing a conduit for information transfer said interface means comprises; control means, responsive to said processor means, for providing at least a first control signal having a first state and a second state; information bus means for transferring of data and program information between said processor means and said memory means under the control of the processor means and memory addressing means including an address register responsive to the control signal when at a first state and a program counter register responsive to the control signal is incremented when the control signal is at a second state, the address register addresses the memory means for the entering or retrieving of data information and the program counter addresses the memory means for the entering and retrieving of program information; and control bus means for transferring of at least the first control signal between said processor means and said memory addressing means.
Claim 2
Dependent Claim
191 words
A digital processor system comprising: memory means for storing of information; processor means for entering and extracting information from the memory means under the control of a predetermined program sequence; interface means coupled between said processor means and memory means for providing a conduit for information transfer said interface means comprises; control means, responsive to said processor means, for providing at least a first control signal having a first state and a second state; information bus means for transferring of data and program information between said processor means and said memory means under the control of the processor means and memory addressing means including an address register responsive to the control signal when at a first state and a program counter register responsive to the control signal is incremented when the control signal is at a second state, the address register addresses the memory means for the entering or retrieving of data information and the program counter addresses the memory means for the entering and retrieving of program information; and control bus means for transferring of at least the first control signal between said processor means and said memory addressing means.
Claim 3
Dependent Claim
20 words
The digital processor system according to claim 1, wherein said memory means includes a memory read and memory write capability.
Claim 4
Dependent Claim
27 words
The digital processor system according to claim 1, wherein said information bus means transfers address information and program and data information on the same information bus lines.
Claim 5
Dependent Claim
24 words
A digital processor system according to claim 3, wherein said information bus means transfers 16 bits of information in two separate 8 bit transfers.
Claim 6
Dependent Claim
51 words
The digital processor system according to claim 1 wherein said memory addressing means comprises: a switching means for selecting either said address register or said program counter register to provide the address to the memory means for the information to be accessed, said switching means being responsive to said control means.
Claim 7
Dependent Claim
42 words
A digital processor system according to claim 5, wherein said control means includes an address strobe signal and a data strobe signal both coupled to said switching means and further including a program counter increment signal coupled to said program counter register.
Claim 8
Dependent Claim
17 words
A digital processor system according to claim 6, wherein said control means further comprises a read/write signal.
References Cited (Backward Citations)
US4161788A
Cited
US4286321A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-10-23 | 1988-04-23 | 1988-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-10-23 | 1992-04-23 | 1992-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-10-23 | 1996-04-23 | 1996-10-23 | $7700.00 | Window Closed / Lapsed |