Microcomputer system

Claim 2

A microcomputer system comprising a microprocessor and a memory chip coupled to the microprocessor though an address/data bus and various control signal lines; said microprocessor being configured to output an address and data through said address/data bus to said memory chip and also to fetch an instruction code and data through said address/data bus from said memory chip, said microprocessor operating to output an address latch signal, a read signal, a write signal, an instruction/data signal and an instruction read signal through said control signal lines to said memory chip; said memory chip including: memory means for storing programs and data and being coupled to receive data from said address/data bus and to output an instruction code and data to said address/data bus, an address latch coupled to latch an address on said address/data bus in response to said address latch signal, an instruction pointer holding an address for an instruction code, an update means coupled to said instruction pointer and operating to output an updated address obtained by changing the address held in said instruction pointer by a predetermined number in response to each instruction read signal when said instruction/data signal designates an instruction, said instruction pointer being updated with said updated address outputted from said update means, selection means coupled to receive the address latched in said address latch and said updated address outputted from said update means and controlled by said instruction/data signal so as to output the address latched in said address latch when said instruction/data signal designates data and said updated address outputted from said update means when said instruction/data signal designates an instruction, and decode means coupled to receive the address outputted from said selection means and to output a decoded address to said memory means so that an instruction code or data is read from said memory means in accordance with the decoded address or data is written to said memory means in accordance with the decoded address, whereby said system being operative such that: when data is written to said memory means, said microprocessor operates to output an address through said address/data bus to said memory chip and also to output such address latch signal to said memory chip so as to cause the address on said address/data bus to be latched in said address latch of said memory chip, and thereafter, to output data through said address/data bus to said memory chip and also to output said instruction/data signal designating the data and said write signal to said memory chip so that the address latched in said address latch is outputted from said selection means and the data on said address/data bus to be written into said memory means in accordance with the address latched in said address latch; when data is read from said memory means, said microprocessor operates to output an address through said address/data bus to said memory chip and also to output said address latch signal to said memory chip so as to cause the address on said address/data bus to be latched in said address of said memory chip, and thereafter, to output data through said address/data bus to said memory chip and also to output said instruction/data signal designating the data and said write signal to said memory chip so that the address latched in said address latch is outputted from said selection means and the data on said address/data bus to be written into said memory means in accordance with the address latched in said address latch; when data is read from said memory means, said microprocessor operates to output an address through said address/data bus to said memory chip and also to output said address latch signal to said memory chip so as to cause the address on said address/data bus to be latched in said address latch of said memory chip, and thereafter, to output said instruction/data signal designating the data and said read signal to said memory chip so that the address latched in said address latch is outputted from said selection means and data is read from said memory means in accordance with the address latched in said address latch so as to be outputted through said address/data bus to said microprocessor; and when instruction codes are read from said memory means, said microprocessor operates to output said instruction/data signal designating the instruction and said read signal to said memory chip and also to intermittently and sequentially output said instruction read signal to said memory chip so that at each time said instruction read signal is outputted from said microprocessor, and address held in said instruction pointer is updated, and an instruction code is read from said memory means in accordance with the updated address, with the result that instruction codes are continuously read from said memory means through said address/data bus to said microprocessor with no address supplied from said microprocessor.

Claim 3

A microcomputer system as claimed in claim 1, wherein said update means includes an incrementer coupled to receive the address held in said instruction pointer and to increment the received address in response to each instruction read signal when said instruction/data signal designates an instruction, said instruction pointer being updated with an incremented address outputted from said incrementer.

Claim 4

A microcomputer system as claimed in claim 1, wherein said memory chip further includes interface means coupled to said address/data bus, and an internal memory address/data bus coupled to said interface means, said memory means being coupled to said internal memory address/data bus so as to receive the data through said interface means from said address/data bus and to output the instruction code and data through said interface means to said address/data bus, and said address latch being coupled to said internal memory address/data bus so as to receive the address on said address/data bus through said interface means.

Claim 5

A microcomputer system as claimed in claim 3, wherein said instruction pointer is coupled to said internal memory address/data bus so as to apply to said internal memory address/data bus start address for a series of continuous instruction codes.

Claim 6

A microcomputer system as claimed in claim 1, wherein said memory means includes a program memory and a data memory which are coupled to receive the address outputted from said decode means, said decode means being connected to receive said instruction/data signal and operating to output the decoded address to said data memory when said instruction/data signal designates the data and to program memory when said instruction/data signal designates the instruction.

Claim 7

A microcomputer system comprising a microprocessor and a memory chip coupled to the microprocessor through an address/data bus and various control signal lines; said microprocessor being configured to output an address and data through said address/data bus to said memory chip and also to fetch an instruction code and data through said address/data bus from said memory chip, said microprocessor operating to output an address latch signal, a read signal, a write signal, an instruction/data signal and an instruction read signal through said control signal lines to said memory chip; said memory chip including: memory means for storing programs and data and being coupled to receive data from said address/data bus and to output an instruction code and data to said address/data bus, an address latch coupled to latch an address on said address/data bus in response to said address latch signal, an instruction pointer for holding an address for an instruction code and coupled to latch an address on said address/data bus in response to said instruction/data signal designating an instruction, an update means coupled to said instruction pointer and operating to output an updated address obtained by changing the address held in said instruction pointer by a predetermined number in response to each instruction read signal when said instruction/data signal designates an instruction, said instruction pointer being updated with said updated address outputted from said update means, selection means coupled to receive the address latched in said address latch and said updated address outputted from said update means and controlled by said instruction/data signal so as to output the address latched in said address latch when said instruction/data signal designates data and said updated address outputted from said update means when said instruction/data signal designates an instruction, and decode means coupled to receive the address outputted from said selection means and to output a decoded address to said memory means so that an instruction code or data is read from said memory means in accordance with the decoded address or data is written to said memory means in accordance with the decoded address; whereby said system being operative such that: when data is written to said memory means, said microprocessor operates to output an address through said address/data bus to said memory chip and also to output said address latch signal to said memory chip so as to cause the address on said address/data bus to be latched in said address latch of said memory chip, and thereafter, to output data through said address/data bus to said memory chip and also to output said instruction/data signal designating the data and said write signal to said memory chip so that the address latched in said address latch is outputted from said selection means and the data on said address/data bus to be written into said memory means in accordance with the address latched in said address latch; when data is read from said memory means, said microprocessor operates to output an address through said address/data bus to said memory chip and also to output said address latch signal to said memory chip so as to cause the address on said address/data bus to be latched in said address latch of said memory chip, and thereafter, to output said instruction/data signal designating the data and said read signal to said memory chip so that the address latched in said address latch is outputted from said selection means and data is read from said memory means in accordance with the address latched in said address latch so as to be outputted through said address/data bus to said microprocessor; and when a branch operation is performed, said microprocessor operates to output a branch address through said address/data bus to said memory chip and also to output said instruction/data signal designating the instruction to said memory chip so as to cause the address on said address/data bus to be latched in said instruction pointer of said memory chip, and thereafter, to maintain said instruction/data signal designating the instruction, to output said read signal to said memory chip and also to intermittently and sequentially output said instruction read signal to said memory chip so that at each time said instruction read signal is outputted from said microprocessor, said address held in said instruction pointer is updated, and an instruction code is read from said memory means in accordance with the updated address, with the result that instruction codes starting at said branch address are continuously read from said memory means through said address/data bus to said microprocessor with no address upplied from said microprocessor.

Claim 8

A microcomputer system comprising a microprocessor and a memory chip coupled to the microprocessor through an address/data bus and various control signal lines; said microprocessor being configured to output an address and data through said address/data bus to said memory chip and also to fetch an instruction code and data through said address/data bus from said memory chip, said microprocessor operating to output an address latch signal, a read signal, a write signal, an instruction/data signal and an instruction read signal through said control signal lines to said memory chip; said memory chip including: memory means for storing programs and data and being coupled to receive data from said address/data bus and to output an instruction code and data to said address/data bus, an address latch coupled to latch an address on said address/data bus in response to said address latch signal, an instruction pointer for holding an address for an instruction code and coupled to latch an address on said address/data bus in response to said instruction/data signal designating an instruction, an update means coupled to said instruction pointer and operating to output an updated address obtained by changing the address held in said instruction pointer by a predetermined number in response to each instruction read signal when said instruction/data signal designates an instruction, said instruction pointer being updated with said updated address outputted from said update means, selection means coupled to receive the address latched in said address latch and said updated address outputted from said update means and controlled by said instruction/data signal so as to output the address latched in said address latch when said instruction/data signal designates data and said updated address outputted from said update means when said instruction/data signal designates an instruction, and decode means coupled to receive the address outputted from said selection means and to output a decoded address to said memory means so that an instruction code or data is read from said memory means in accordance with the decoded address or data is written to said memory means in accordance with the decoded address; whereby said system being operative such that: when data is written to said memory means, said microprocessor operates to output an address through said address/data bus to said memory chip and also to output said address latch signal to said memory chip so as to cause the address on said address/data bus to be latched in said address latch of said memory chip, and thereafter, to output data through said address/data bus to said memory chip and also to output said instruction/data signal designating the data and said write signal to said memory chip so that the address latched in said address latch is outputted from said selection means and the data on said address/data bus to be written into said memory means in accordance with the address latched in said address latch; when data is read from said memory means, said microprocessor operates to output an address through said address/data bus to said memory chip and also to output said address latch signal to said memory chip so as to cause the address on said address/data bus to be latched in said address latch of said memory chip, and thereafter, to output said instruction/data signal designating the data and said read signal to said memory chip so that the address latched in said address latch is outputted from said selection means and data is read from said memory means in accordance with the address latched in said address latch so as to be outputted through said address/data bus to said microprocessor; and when a branch operation is performed, said microprocessor operates to output a branch address through said address/data bus to said memory chip and also to output said instruction/data signal designating the instruction to said memory chip so as to cause the address on said address/data bus to be latched in said instruction pointer of said memory chip, and thereafter, to maintain said instruction/data signal designating the instruction, to output said read signal to said memory chip and also to intermittently and sequentially output said instruction read signal to said memory chip so that at each time said instruction read signal is outputted from said microprocessor, said address held in said instruction pointer is updated, and an instruction code is read from said memory means in accordance with the updated address, with the result that instruction codes starting at said branch address are continuously read from said memory means through said address/data bus to said microprocessor with no address upplied from said microprocessor.

Claim 9

A microcomputer system as claimed in claim 6, wherein said update means includes an incrementer coupled to receive the address held in said instruction pointer and to increment the received address in response to each instruction read signal when said instruction/data signal designates an instruction, said instruction pointer being updated with an incremented address outputted from said incrementer.

Claim 10

A microcomputer system as claimed in claim 6, wherein said memory chip further includes interface means coupled to said address/data bus, and an internal memory address/data bus coupled to said interface means, said memory means being coupled to said internal memory address/data bus so as to receive the data through said interface means from said address/data bus and to output the instruction code and data through said interface means to said address/data bus, and said address latch being coupled to said internal memory address/data bus so as to receive the address on said address/data bus through said interface means.

Claim 11

A microcomputer system as claimed in claim 8, wherein said instruction pointer is coupled to said internal memory address/data bus so as to apply to said internal memory address/data bus said branch address.

Claim 12

A microcomputer system as claimed in claim 6, wherein said memory means includes a program memory and a data memory which are coupled to receive the address outputted from said decode means, said decode means being connected to receive said instruction/data signal and operating to output the decoded address to said data memory when said instruction/data signal designates the data and to program memory when said instruction/data signal designates the instruction.

Claim 13

A microcomputer system comprising a microprocessor and a memory chip coupled to the microprocessor through an address/data bus and various control signal lines; said microprocessor being configured to output an address and data through said address/data bus to said memory chip and also to fetch an instruction code and data through said address/data bus from said memory chip, said microprocessor operating to output an address latch signal, a read signal, a write signal, an instruction/data signal and an instruction read signal through said control signal lines to said memory chip; said memory chip including: memory means for storing programs and data and being coupled to receive data from said address/data bus and to output an instruction code and data to said address/data bus, an address latch coupled to latch an address on said address/data bus in response to said address latch signal, an instruction pointer for holding an address for an instruction code and coupled to latch an address on said address/data bus in response to said instruction/data signal designating an instruction, an update means coupled to said instruction pointer and operating to output an updated address obtained by changing the address held in said instruction pointer by a predetermined number in response to each instruction read signal when said instruction/data signal designates an instruction, said instruction pointer being updated with said updated address outputted from said update means, selection means coupled to receive the address latched in said address latch and said updated address outputted from said update means and controlled by said instruction/data signal so as to output the address latched in said address latch when said instruction/data signal designates data and said updated address outputted from said update means when said instruction/data signal designates an instruction, and decode means coupled to receive the address outputted from said selection means and to output a decoded address to said memory means so that an instruction code or data is read from said memory means in accordance with the decoded address or data is written to said memory means in accordance with the decoded address, whereby said system being operative such that: when data is written to said memory means, said microprocessor operates to output an address through said address/data bus to said memory chip and also to output said address latch signal to said memory chip so as to cause the address on said address/data bus to be latched in said address latch of said memory chip, and thereafter, to output data through said address/data bus to said memory chip and also to output said instruction/data signal designating the data and said write signal to said memory chip so that the address latched in said address latch is outputted from said selection means and the data on said address/data bus to be written into said memory means in accordance with the address latched in said address latch; when data is read from said memory means, said microprocessor operates to output an address through said address/data bus to said memory chip and also to output said address latch signal to said memory chip so as to cause the address on said address/data bus to be latched in said address latch of said memory chip, and thereafter, to output said instruction/data signal designating the data and said read signal to said memory chip so that the address latched in said address latch is outputted from said selection means and data is read from said memory means in accordance with the address latched in said address latch so as to be outputted through said address/data bus to said microprocessor; when instruction codes are read from said memory means, said microprocessor operates to output said instruction/data signal designating the instruction and said read signal to said memory chip and also to intermittently and sequentially output said instruction read signal to said memory chip so that at each time said instruction read signal is outputted from said microprocessor, said address held in said instruction pointer is updated, and an instruction code is read from said memory means in accordance with the updated address, with the result that instruction codes are continuously read from said memory means through said address/data bus to said microprocessor with no address supplied from said microprocessor; and when a branch operation is performed, said microprocessor operates to output a branch address through said address/data bus to said memory chip and also to output said instruction/data signal designating the instruction to said memory chip so as to cause the address on said address/data bus to be latched in said instruction pointer of said memory chip, and thereafter, to maintain said instruction/data signal designating the instruction, to output read signal to said memory chip and also to intermittently and sequentially output said instruction read signal to said memory chip so that at each time said instruction read signal is outputted from said microprocessor, said address held in said instruction pointer is updated, and an instruction code is read from said memory means in accordance with the updated address, with the result that instruction codes starting at said branch address are continuously read from said memory means through said address/data bus to said microprocessor with no address supplied from said microprocessor.

Claim 14

A microcomputer system comprising a microprocessor and a memory chip coupled to the microprocessor through an address/data bus and various control signal lines; said microprocessor being configured to output an address and data through said address/data bus to said memory chip and also to fetch an instruction code and data through said address/data bus from said memory chip, said microprocessor operating to output an address latch signal, a read signal, a write signal, an instruction/data signal and an instruction read signal through said control signal lines to said memory chip; said memory chip including: memory means for storing programs and data and being coupled to receive data from said address/data bus and to output an instruction code and data to said address/data bus, an address latch coupled to latch an address on said address/data bus in response to said address latch signal, an instruction pointer for holding an address for an instruction code and coupled to latch an address on said address/data bus in response to said instruction/data signal designating an instruction, an update means coupled to said instruction pointer and operating to output an updated address obtained by changing the address held in said instruction pointer by a predetermined number in response to each instruction read signal when said instruction/data signal designates an instruction, said instruction pointer being updated with said updated address outputted from said update means, selection means coupled to receive the address latched in said address latch and said updated address outputted from said update means and controlled by said instruction/data signal so as to output the address latched in said address latch when said instruction/data signal designates data and said updated address outputted from said update means when said instruction/data signal designates an instruction, and decode means coupled to receive the address outputted from said selection means and to output a decoded address to said memory means so that an instruction code or data is read from said memory means in accordance with the decoded address or data is written to said memory means in accordance with the decoded address, whereby said system being operative such that: when data is written to said memory means, said microprocessor operates to output an address through said address/data bus to said memory chip and also to output said address latch signal to said memory chip so as to cause the address on said address/data bus to be latched in said address latch of said memory chip, and thereafter, to output data through said address/data bus to said memory chip and also to output said instruction/data signal designating the data and said write signal to said memory chip so that the address latched in said address latch is outputted from said selection means and the data on said address/data bus to be written into said memory means in accordance with the address latched in said address latch; when data is read from said memory means, said microprocessor operates to output an address through said address/data bus to said memory chip and also to output said address latch signal to said memory chip so as to cause the address on said address/data bus to be latched in said address latch of said memory chip, and thereafter, to output said instruction/data signal designating the data and said read signal to said memory chip so that the address latched in said address latch is outputted from said selection means and data is read from said memory means in accordance with the address latched in said address latch so as to be outputted through said address/data bus to said microprocessor; when instruction codes are read from said memory means, said microprocessor operates to output said instruction/data signal designating the instruction and said read signal to said memory chip and also to intermittently and sequentially output said instruction read signal to said memory chip so that at each time said instruction read signal is outputted from said microprocessor, said address held in said instruction pointer is updated, and an instruction code is read from said memory means in accordance with the updated address, with the result that instruction codes are continuously read from said memory means through said address/data bus to said microprocessor with no address supplied from said microprocessor; and when a branch operation is performed, said microprocessor operates to output a branch address through said address/data bus to said memory chip and also to output said instruction/data signal designating the instruction to said memory chip so as to cause the address on said address/data bus to be latched in said instruction pointer of said memory chip, and thereafter, to maintain said instruction/data signal designating the instruction, to output read signal to said memory chip and also to intermittently and sequentially output said instruction read signal to said memory chip so that at each time said instruction read signal is outputted from said microprocessor, said address held in said instruction pointer is updated, and an instruction code is read from said memory means in accordance with the updated address, with the result that instruction codes starting at said branch address are continuously read from said memory means through said address/data bus to said microprocessor with no address supplied from said microprocessor.

Claim 15

A microprocessor system as claimed in claim 11, wherein said update means includes an incrementer coupled to receive the address held in said instruction pointer and to increment the received address in response to each instruction read signal when said instruction/data signal designates an instruction, said instruction pointer being updated with an incremented address outputted from said incrementer.

Claim 16

A microcomputer system as claimed in claim 11, wherein said memory chip further includes interface means coupled to said address/data bus, and an internal memory address/data bus coupled to said interface means, said memory means being coupled to said internal memory address/data bus so as to receive the data through said interface means from said address/data bus and to output the instruction code and data through said interface means to said address/data bus, and said address latch being coupled to said internal memory address/data bus so as to receive the address on said address/data bus through said interface means.

Claim 17

A microcomputer system as claimed in claim 13, wherein said instruction pointer is coupled to said internal memory address/data bus so as to apply to said internal memory address/data bus said branch address.

Claim 18

A microcomputer system as claimed in claim 11, wherein said memory means includes a program memory and a data memory which are coupled to receive the address outputted from said decode means, said decode means being connected to receive said instruction/data signal and operating to output the decoded address to said data memory when said instruction/data signal designates the data and to program memory when said instruction/data signal designates the instruction.

Claim 19

A memory chip coupled to an address/data bus so as to receive an address and data and to output an instruction code and data in response to various control signals including an address latch signal, a read signal, a write signal, an instruction/data signal and an instruction read signal, comprising: memory means for storing programs and data and being coupled to receive data from said address/data bus and to output an instruction code and data to said address/data bus, an address latch coupled to latch an address on said address/data bus in response to said address latch signal, an instruction pointer holding an address for an instruction code, an update means coupled to said instruction pointer and operating to output an updated address obtained by changing the address held in said instruction pointer by a predetermined number in response to each instruction read signal when said instruction/data signal designates an instruction, said instruction pointer being updated with said updated address outputted from said update means, selection means coupled to receive the address latched in said address latch and said updated address outputted from said update means and controlled by said instruction/data signal so as to output the address latched in said address latch when said instruction/data signal designates an instruction, and decode means coupled to receive the address outputted from said selection means and to output a decoded address to said memory means so that an instruction code or data is read from said memory means in accordance with the decoded address or data is written to said memory means in accordance with the decoded address, whereby said system being operative such that: when data is written to said memory means, the memory chip receives an address through said address/data bus and said address latch signal so that the address on said address/data bus is latched in said address latch, and thereafter, the memory chip receives data through said address/data bus and also receives said instruction/data signal designating the data and said write signal so that the address latched in said address latch is outputted from said selection means and the data on said address/data bus to be written into said memory means in accordance with the address latched in said address latch; when data is read from said memory means, the memory chip receives an address through said address/data bus and said address latch signal so that the address on said address/data bus is latched in said address latch, and thereafter, the memory chip receives said instruction/data signal designating the data and said read signal so that the address latched in said address latch is outputted from said selection means and data is read from said memory means in accordance with the address latched in said address latch so as to be outputted through said address/data bus to said microprocessor; and when instruction codes are read from said memory means, the memory chip receives said instruction/data signal and also receives intermittently and sequentially said instruction read signal so that at each time said instruction read signal is received, said address held in said instruction pointer is updated, and an instruction code is read from said memory means in accordance with the updated address, with the result that instruction codes are continuously read from said memory means through said address/data bus with no address supplied from an external device.

Claim 20

A memory chip coupled to an address/data bus so as to receive an address and data and to output an instruction code and data in response to various control signals including an address latch signal, a read signal, a write signal, an instruction/data signal and an instruction read signal, comprising: memory means for storing programs and data and being coupled to receive data from said address/data bus and to output an instruction code and data to said address/data bus, an address latch coupled to latch an address on said address/data bus in response to said address latch signal, an instruction pointer holding an address for an instruction code, an update means coupled to said instruction pointer and operating to output an updated address obtained by changing the address held in said instruction pointer by a predetermined number in response to each instruction read signal when said instruction/data signal designates an instruction, said instruction pointer being updated with said updated address outputted from said update means, selection means coupled to receive the address latched in said address latch and said updated address outputted from said update means and controlled by said instruction/data signal so as to output the address latched in said address latch when said instruction/data signal designates an instruction, and decode means coupled to receive the address outputted from said selection means and to output a decoded address to said memory means so that an instruction code or data is read from said memory means in accordance with the decoded address or data is written to said memory means in accordance with the decoded address, whereby said system being operative such that: when data is written to said memory means, the memory chip receives an address through said address/data bus and said address latch signal so that the address on said address/data bus is latched in said address latch, and thereafter, the memory chip receives data through said address/data bus and also receives said instruction/data signal designating the data and said write signal so that the address latched in said address latch is outputted from said selection means and the data on said address/data bus to be written into said memory means in accordance with the address latched in said address latch; when data is read from said memory means, the memory chip receives an address through said address/data bus and said address latch signal so that the address on said address/data bus is latched in said address latch, and thereafter, the memory chip receives said instruction/data signal designating the data and said read signal so that the address latched in said address latch is outputted from said selection means and data is read from said memory means in accordance with the address latched in said address latch so as to be outputted through said address/data bus to said microprocessor; and when instruction codes are read from said memory means, the memory chip receives said instruction/data signal and also receives intermittently and sequentially said instruction read signal so that at each time said instruction read signal is received, said address held in said instruction pointer is updated, and an instruction code is read from said memory means in accordance with the updated address, with the result that instruction codes are continuously read from said memory means through said address/data bus with no address supplied from an external device.

Claim 21

A memory chip as claimed in claim 16, wherein said update means includes an incrementer coupled to receive the address held in said instruction pointer and to increment the received address in response to each instruction read signal when said instruction/data signal designates an instruction, said instruction pointer being updated with an incremented address outputted from said incrementer.

Claim 22

A memory chip as claimed in claim 16, further including interface means coupled to said address/data bus, and an internal memory address/data bus coupled to said interface means, said memory means being coupled to said internal memory address/data bus so as to receive the data through said interface means from said address/data bus and to output the instruction code and data through said interface means to said address/data bus, and said address latch being coupled to said internal memory address/data bus so as to receive the address on said address/data bus through said interface means.

Claim 23

A memory chip as claimed in claim 18, wherein said instruction pointer is coupled to said internal memory address/data bus so as to apply to said internal memory address/data bus start address for a series of continuous instruction codes.

Claim 24

A memory chip as claimed in claim 16, wherein said memory means includes a program memory and a data memory which are coupled to receive the address outputted from said decode means, said decode means being connected to receive said instruction/data signal and operating to output the decoded address to said data memory when said instruction/data signal designates the data and to program memory when said instruction/data signal designates the instruction.