Circuit for cancelling and replacing redundant elements

Claim 2

An integrated circuit having a plurality of selectively addressable primary elements and a plurality of selectively programmable redundant elements, the integrated circuit comprising; a redundant element enable circuit connected to one of the plurality of selectively programmable redundant elements; a redundant element program circuit connected to the one of the plurality of selectively programmable redundant elements and used to selectively program the one of the plurality of selectively programmable redundant elements to replace a defective one of the plurality of selectively addressable primary elements; and a non-volatile redundant element disable circuit connected to the redundant element enable circuit, the non-volatile redundant element disable circuit adopted to disable the one of the plurality of selectively programmable redundant elements.

Claim 3

The integrated circuit of claim 1 where the integrated circuit comprises an integrated circuit memory array, and the plurality of selectively addressable primary elements are a plurality of selectively addressable primary memory elements and the plurality of selectively programmable redundant elements are a plurality of selectively programmable redundant memory elements.

Claim 4

The integrated circuit of claim 1 where the non-volatile redundant element disable circuit comprises a selectively blowable fuse.

Claim 5

The integrated circuit of claim 1 where the non-volatile redundant element disable circuit comprises; a latch circuit which produces an output that indicates when an enabled one of the plurality of selectively programmable redundant elements is addressed; and a fuse circuit which produces a pre-determined output used to permanently disable the enabled one of the plurality of selectively addressable redundant elements.

Claim 6

The integrated circuit of claim 4 where the fuse circuit comprises a selectively blowable anti-fuse.

Claim 7

The integrated circuit of claim 4 where the fuse circuit comprises a selectively blowable anti-fuse electrically connected to a low voltage level through at least one high voltage transistor.

Claim 8

The integrated circuit of claim 6 where the at least one high voltage transistor is fabricated using a field isolation implant technique.

Claim 9

An integrated circuit memory array having a plurality of selectively addressable primary memory elements and a plurality of selectively programmable redundant memory elements, the integrated circuit memory comprising; a non-volatile redundant memory element enable circuit connected to one of the plurality of selectively programmable redundant elements; a redundant element program circuit connected to the one of the plurality of selectively programmable redundant memory elements and used to selectively program the one of the plurality of selectively programmable redundant memory elements to replace a defective one of the plurality of selectively addressable primary memory elements; and a non-volatile redundant memory element disable circuit connected to the non-volatile redundant memory element enable circuit, the non-volatile redundant memory element disable circuit adapted to disable the one of the plurality of selectively programmable redundant memory elements.

Claim 10

An integrated circuit memory array having a plurality of selectively addressable primary memory elements and a plurality of selectively programmable redundant memory elements, the integrated circuit memory comprising; a non-volatile redundant memory element enable circuit connected to one of the plurality of selectively programmable redundant elements; a redundant element program circuit connected to the one of the plurality of selectively programmable redundant memory elements and used to selectively program the one of the plurality of selectively programmable redundant memory elements to replace a defective one of the plurality of selectively addressable primary memory elements; and a non-volatile redundant memory element disable circuit connected to the non-volatile redundant memory element enable circuit, the non-volatile redundant memory element disable circuit adapted to disable the one of the plurality of selectively programmable redundant memory elements.

Claim 11

The integrated circuit memory array of claim 8 where the non-volatile redundant memory element enable circuit comprises a selectively blowable fuse.

Claim 12

The integrated circuit memory array of claim 8 where the disable circuit comprises; a latch circuit which produces an output that indicates when an enabled one of the plurality of selectively programmable redundant memory elements is addressed; and a fuse circuit which produces a pre-determined output used to permanently disable the enabled one of the plurality of selectively programmable redundant memory elements.

Claim 13

The integrated circuit memory array of claim 10 where the fuse circuit comprises a selectively blowable anti-fuse.

Claim 14

The integrated circuit memory array of claim 10 where the fuse circuit comprises a selectively blowable anti-fuse electrically connected to a low voltage level through at least one high voltage transistor.

Claim 15

The integrated circuit of claim 12 where the at least one high voltage transistor is fabricated using a field isolation implant technique.

Claim 16

The integrated circuit memory array of claim 8 where the redundant element program circuit comprises; a plurality of address line inputs; and a plurality of selectively blowable fuses associated with the plurality of address line inputs which allow the redundant element program circuit to respond to a pre-determined address provided on the plurality of address line inputs.