US5325334A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Column redundancy circuit for a semiconductor memory device
Assignee: Samsung Electronics Co Ltd
•
Filing: 1993-02-05
•
Granted: 1994-06-28
•
Expires: 2013-02-05
Abstract
Abstract A column redundancy circuit for a semiconductor memory device, e.g., a DRAM, which includes a normal memory array comprised of a plurality of memory blocks each comprised of a matrix of rows and columns of memory cells, with at least two of the memory blocks sharing common columns, and with at least one of the columns being defective, in the sense of being connected to at least one memory cell which has been determined to be defective. The column redundancy circuit includes a plurality of redundant columns, block selection control circuit which is programmed to generate a first output signal in response to receipt of a memory block address signal corresponding to one or more of the memory blocks which contain the defective column, a column address decoder which is programmed to generate a second output signal in response to receipt of both the first output signal and a column address signal corresponding to the defective column, and, a redundant column driver circuit which is responsive to the second output signal for activating a predetermined one of the redundant columns, to thereby repair the defective column. In a preferred embodiment, the block selection control circuit and the column address decoder each include a plurality of fuses and are each programmed by means of a selected one or more of their fuses being blown, e.g., by use of a laser.
Inventors
- 👤 Jae-Gu Roh
- 👤 Yong-sik Seok
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 08:54
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/80; G11C29/808
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
204 words
A column redundancy circuit for a semiconductor memory device including a normal memory array comprised of a plurality of memory blocks each comprised of a matrix of rows and columns of memory cells, with at least two of the memory blocks sharing common columns, and with at least one of the columns being defective, in the sense of being connected to at least one memory cell which has been determined to be defective, the column redundancy circuit comprising: a plurality of redundant columns; block selection control circuit means programmed to generate a first output signal in response to receipt of a memory block address signal corresponding to one or more of said memory blocks which contain said defective column, wherein said block selection control circuit means includes a plurality of fuses and is programmed by means of a selected one or more of said fuses being blown; column address decoder means programmed to generate a second output signal in response to receipt of both said first output signal and a column address signal corresponding to said defective column; and, redundant column driver means responsive to said second output signal for activating a predetermined one of said redundant columns, to thereby repair said defective column.
Claim 2
Dependent Claim
204 words
A column redundancy circuit for a semiconductor memory device including a normal memory array comprised of a plurality of memory blocks each comprised of a matrix of rows and columns of memory cells, with at least two of the memory blocks sharing common columns, and with at least one of the columns being defective, in the sense of being connected to at least one memory cell which has been determined to be defective, the column redundancy circuit comprising: a plurality of redundant columns; block selection control circuit means programmed to generate a first output signal in response to receipt of a memory block address signal corresponding to one or more of said memory blocks which contain said defective column, wherein said block selection control circuit means includes a plurality of fuses and is programmed by means of a selected one or more of said fuses being blown; column address decoder means programmed to generate a second output signal in response to receipt of both said first output signal and a column address signal corresponding to said defective column; and, redundant column driver means responsive to said second output signal for activating a predetermined one of said redundant columns, to thereby repair said defective column.
Claim 3
Dependent Claim
25 words
The column redundancy circuit as set forth in claim 1, wherein said block selection control circuit means comprises a plurality of individually programmed decoder units.
Claim 4
Dependent Claim
21 words
The column redundancy circuit as set forth in claim 2, wherein each of said decoder units includes a plurality of fuses.
Claim 5
Dependent Claim
37 words
The column redundancy circuit as set forth in claim 1, wherein said column address decoder means includes a plurality of fuses and is programmed by means of a selected one or more of said fuses being blown.
Claim 6
Dependent Claim
43 words
The column redundancy circuit as set forth in claim 4, wherein said normal memory array is a multi-tiered memory array including a plurality of sub-arrays ranging from largest sub-array units A,/A to smallest sub-array units Z,/Z nested within said largest sub-array units A,/A.
Claim 7
Dependent Claim
137 words
The column redundancy circuit as set forth in claim 2, wherein each of said individually programmed decoder units comprises: a control terminal connected to a source of static voltage; a memory block address signal terminal for receiving a memory block address signal identifying one or more of said memory blocks; a control node; switching means having a first electrode portion connected to said control and memory block address signal terminals and a second electrode portion; a control fuse connected between said second electrode portion of said switching means and said control node; a programming fuse connected between said second electrode portion of said switching means and said control node; and, wherein said block selection control circuit means is programmed by means of a selected one or more of said control fuses and said programming fuses being blown.
Claim 8
Dependent Claim
43 words
The column redundancy circuit as set forth in claim 6, wherein said normal memory array is a multi-tiered memory array including a plurality of sub-arrays ranging from largest sub-array units A,/A to smallest sub-array units Z,/Z nested within said largest sub-array units A,/A.
Claim 9
Dependent Claim
28 words
The column redundancy circuit as set forth in claim 6, further comprising signal generating means responsive to receipt of a row address signal for generating an enable signal.
Claim 10
Dependent Claim
28 words
The column redundancy circuit as set forth in claim 8, wherein said row address signal corresponds to that of a defective memory call connected to said defective column.
Claim 11
Dependent Claim
25 words
The column redundancy circuit as set forth in claim 8, wherein said switching means is turned on in response to receipt of said enable signal.
Claim 12
Dependent Claim
25 words
The column redundancy circuit as set forth in claim 6, wherein said source of static voltage comprises the power supply voltage of said memory device.
Claim 13
Dependent Claim
21 words
The column redundancy circuit as set forth in claim 11, wherein said memory device comprises a dynamic random access memory device.
Claim 14
Dependent Claim
191 words
The column redundancy circuit as set forth in claim 2, wherein each of said decoder units comprises: a control terminal connected to a static voltage; a first memory block address signal terminal adapted to receive a first memory block address signal identifying a first one of said memory blocks; a second memory block address signal terminal adapted to receive a second memory block address signal identifying a second one of said memory blocks; a control node; switching means having a first electrode portion connected to said control and first and second memory block address signal terminals, and a second electrode portion; a control fuse connected between said second electrode portion of said switching means and said control node; a first programming fuse connected between said second electrode portion of said switching means and said control node; a second programming fuse connected between said second electrode portion of said switching means and said control node; and wherein said block selection control circuit means is programmed by means of a selected one or more of said control fuses and a selected one or more of said first and second programming fuses being blown.
Claim 15
Dependent Claim
41 words
The column redundancy circuit as set forth in claim 13, further comprising logic gate means having a plurality of inputs connected to said control node of respective ones of said individually programmed decoder units of said block selection control circuit means.
Claim 16
Dependent Claim
34 words
The column redundancy circuit as set forth in claim 14, wherein said logic gate means is responsive to said control nodes all going to the same logic level for generating said first output signal.
Claim 17
Dependent Claim
37 words
The column redundancy circuit as set forth in claim 15, wherein said column address decoder means includes a plurality of fuses and is programmed by means of a selected one or more of said fuses being blown.
Claim 18
Dependent Claim
28 words
The column redundancy circuit as set forth in claim 16, further comprising signal generating means responsive to receipt of a row address signal for generating an enable signal.
Claim 19
Dependent Claim
25 words
The column redundancy circuit as set forth in claim 17, wherein said switching means is turned on in response to receipt of said enable signal.
Claim 20
Dependent Claim
27 words
The column redundancy circuit as set forth in claim 13, wherein said control and first and second programming fuses are selectively blown by means of a laser.
References Cited (Backward Citations)
US4758993A
Cited
US4827747A
Cited
US4829480A
Cited
US5193076A
Cited
US5033024A
Cited
US5210723A
Cited
US5159572A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-06-27 | 1997-12-27 | 1998-06-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-06-27 | 2001-12-27 | 2002-06-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-06-27 | 2005-12-27 | 2006-06-28 | $7700.00 | Window Closed / Lapsed |