Semiconductor processing methods of forming field oxidation regions on a semiconductor substrate

Claim 2

A semiconductor processing method of forming a pair of adjacent field oxide regions having a minimum pitch of from 0.5 micron to 0.7 micron on a semiconductor substrate, the method comprising the following steps: forming a sacrificial pad oxide layer over a semiconductor substrate to a thickness of from 20 Angstroms to 100 Angstroms; forming a patterned masking layer over the sacrificial pad oxide layer and over a desired active area region of the substrate, the masking layer comprising a nitride and having a thickness of from 500 Angstroms to 3000 Angstroms, the patterned masking layer comprising a pair of adjacent masking blocks having a minimum pitch of from 0.5 micron to 0.7 micron; oxidizing portions of the substrate unmasked by the masking layer in an H 2 O steam comprising ambient at a pressure of from about 0.5 atmosphere to about 2 atmospheres and at a temperature of from about 900° C. to about 1200° C. to form at least one pair of adjacent field oxide regions on the subsrate, the formed field oxide regions having a location of maximum thickness of from 1500 Angstroms to 3000 Angstroms, the pair of field oxide regions defining an active area therebetween; removing the patterned masking layer from the substrate; removing the sacrificial pad oxide layer from over the active area between the pair of field oxide regions; forming a gate oxide layer on the substrate over the active area between the pair of field oxide regions; and etching portions of the pair of field oxide regions prior to forming the gate oxide layer, such etching resulting in removal of a total of from 250 Angstroms to 1000 Angstroms of oxide from the field oxide regions prior to provision of the gate oxide layer, such etching resulting in a maximum width of the respective field oxide regions of from 0.20 micron to 0.40 micron and a minimum pitch of the adjacent pair of field oxide regions of from 0.5 micron to 0.7 micron.

Claim 3

The semiconductor processing method of claim 1 wherein the step of removing the sacrificial pad oxide layer also comprises etching from 50 Angstroms to 500 Angstroms of the field oxide regions.

Claim 4

The semiconductor processing method of claim 1 wherein the sacrificial pad oxide layer is formed to a thickness of less than or equal to 60 Angstroms, and the masking layer is provided to a thickness of from 500 Angstroms to 1000 Angstroms.

Claim 5

The semiconductor processing method of claim 1 wherein the sacrificial pad oxide layer is provided to a thickness of greater than 60 Angstroms, and the masking layer is provided to a thickness of from 1000 Angstroms to 3000 Angstroms.

Claim 6

The semiconductor processing method of claim 1 wherein the sacrificial pad oxide layer is provided to a thickness of 60 Angstroms, and the masking layer is provided to a thickness of 1900 Angstroms.

Claim 7

The semiconductor processing method of claim 1 wherein the step of removing the sacrificial pad oxide layer also comprises etching from 50 Angstroms to 500 Angstroms of the field oxide regions; and wherein the sacrificial pad oxide layer is provided to a thickness of less than or equal to 60 Angstroms, and the masking layer is provided to a thickness of from 500 Angstroms to 1000 Angstroms.

Claim 8

The semiconductor-processing method of claim 1 wherein the step of removing the sacrificial pad oxide layer also comprises etching from 50 Angstroms to 500 Angstroms of the field oxide regions; and wherein the sacrificial pad oxide layer is provided to a thickness of greater than 60 Angstroms, and the masking layer is provided to a thickness of from 1000 Angstroms to 3000 Angstroms.

Claim 9

The semiconductor processing method of claim 1 wherein the step of removing the sacrificial pad oxide layer also comprises etching from 50 Angstroms to 500 Angstroms of the field oxide regions; and wherein the sacrificial pad oxide layer is provided to a thickness of about 60 Angstroms, and the masking layer is provided to a thickness of about 1900 Angstroms.

Claim 10

The semiconductor processing method of claim 1 wherein the pressure during the oxidizing step is about 1 atmosphere.

Claim 11

The semiconductor processing method of claim 1 wherein the temperature during the oxidizing step is from about 1050° C. to about 1100° C.

Claim 12

The semiconductor processing method of claim 1 wherein the pressure during the oxidizing step is about 1 atmosphere, and the temperature during the oxidizing step is from about 1050° C. to about 1100° C.

Claim 13

A semiconductor processing method of forming a pair of adjacent field oxide regions having a minimum pitch of from 0.5 micron to 0.7 micron on a semiconductor substrate, the method comprising the following steps: forming a sacrificial pad oxide layer over a semiconductor substrate to a thickness of from 50 Angstroms to 70 Angstroms; forming a patterned masking layer over the sacrificial pad oxide layer and over a desired active area region of the substrate, the masking layer comprising a nitride and having a thickness of from 1700 Angstroms to 2100 Angstroms, the patterned masking layer comprising a pair of adjacent masking blocks having a minimum pitch of from 0.5 micron to 0.7 micron; oxidizing portions of the substrate unmasked by the masking layer in an H 2 O steam comprising ambient at a pressure of from about 0.8 atmosphere to about 1.2 atmospheres and at a temperature of from about 1000° C. to about 1150° C. to from at least one pair of adjacent field oxide regions on the substrate, the formed field oxide regions having a location of maximum thickness of from 2000 Angstroms to 2400 Angstroms, the pair of field oxide regions defining an active area therebetween; removing the patterned masking layer from the substrate; removing the sacrificial pad oxide layer from over the active area between the pair of fiend oxide regions; forming a gate oxide layer on the substrate over the active area between the pair of field oxide regions; and etching portions of the pair of field oxide regions prior to providing the gate oxide layer, such etching resulting in removal of a total of from 250 Angstroms to 1000 Angstroms of oxide from the field oxide regions prior to provision of the gate oxide layer, such etching resulting in a maximum width of the respective field oxide regions of from 0.20 micron to 0.40 micron and a minimum pitch of the adjacent pair of field oxide regions of from 0.5 micron to 0.7 micron.

Claim 14

A semiconductor processing method of forming a pair of adjacent field oxide regions having a minimum pitch of from 0.5 micron to 0.7 micron on a semiconductor substrate, the method comprising the following steps: forming a sacrificial pad oxide layer over a semiconductor substrate to a thickness of from 50 Angstroms to 70 Angstroms; forming a patterned masking layer over the sacrificial pad oxide layer and over a desired active area region of the substrate, the masking layer comprising a nitride and having a thickness of from 1700 Angstroms to 2100 Angstroms, the patterned masking layer comprising a pair of adjacent masking blocks having a minimum pitch of from 0.5 micron to 0.7 micron; oxidizing portions of the substrate unmasked by the masking layer in an H 2 O steam comprising ambient at a pressure of from about 0.8 atmosphere to about 1.2 atmospheres and at a temperature of from about 1000° C. to about 1150° C. to from at least one pair of adjacent field oxide regions on the substrate, the formed field oxide regions having a location of maximum thickness of from 2000 Angstroms to 2400 Angstroms, the pair of field oxide regions defining an active area therebetween; removing the patterned masking layer from the substrate; removing the sacrificial pad oxide layer from over the active area between the pair of fiend oxide regions; forming a gate oxide layer on the substrate over the active area between the pair of field oxide regions; and etching portions of the pair of field oxide regions prior to providing the gate oxide layer, such etching resulting in removal of a total of from 250 Angstroms to 1000 Angstroms of oxide from the field oxide regions prior to provision of the gate oxide layer, such etching resulting in a maximum width of the respective field oxide regions of from 0.20 micron to 0.40 micron and a minimum pitch of the adjacent pair of field oxide regions of from 0.5 micron to 0.7 micron.

Claim 15

The semiconductor processing method of claim 12 wherein the step of removing the pad oxide also comprises etching from 50 Angstroms to 500 Angstroms of the field oxide regions.

Claim 16

The semiconductor processing method of claim 12 wherein the sacrificial pad oxide layer is provided to a thickness of about 60 Angstroms.

Claim 17

The semiconductor processing method of claim 12 wherein the masking layer is provided to a thickness of about 1900 Angstroms.

Claim 18

The semiconductor processing method of claim 12 wherein the formed field oxide regions have a location of maximum thickness of about 2200 Angstroms.

Claim 19

The semiconductor processing method of claim 12 wherein the sacrificial pad oxide layer is provided to a thickness of 60 Angstroms, and the masking layer is provided to a thickness of 1900 Angstroms.

Claim 20

The semiconductor processing method of claim 12 wherein the sacrificial pad oxide layer is provided to a thickness of about 60 Angstroms, and the formed field oxide regions have a location of maximum thickness of about 2200 Angstroms.

Claim 21

The semiconductor processing method of claim 12 wherein the masking layer is provided to a thickness of about 1900 Angstroms, and the formed field oxide regions have a location of maximum thickness of about 2200 Angstroms.

Claim 22

The semiconductor processing method of claim 12 wherein the sacrificial pad oxide layer is provided to a thickness of 60 Angstroms, the masking layer is provided to a thickness of 1900 Angstroms, and the formed field oxide regions have a location of maximum thickness of about 2200 Angstroms.