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US5393694A Expired / Lapsed US ⏱️ 0.0 years remaining

Advanced process for recessed poly buffered locos

Assignee: Micron Technology Inc
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Filing: 1994-06-15
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Granted: 1995-02-28
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Expires: 2014-06-15
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Abstract

Abstract A process useful for isolating active areas of semiconductor devices, comprising the steps of: forming pad oxide, polysilicon, and nitride layers superjacent a substrate; patterning and etching the layers and the substrate, thereby forming a recess in the substrate; forming a nitride spacer within the recess, then growing a field oxide region therein; removing the layers thereby causing an indentation to form within the periphery of the field oxide region; disposing polysilicon within the indentation; etching the polysilicon to a level even with the field oxide region; and oxidizing the polysilicon.

Inventors

  • 👤 Viju K. Mathews

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 03:43
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0121; H10W10/10; H10W10/13

Claims Analysis

Total Claims: 23
Claim 1
Independent Claim 111 words
A method for forming an isolation device comprising the following steps of: providing a semiconductor substrate having a surface; forming a plurality of layers on the surface of said semiconductor substrate; patterning and etching said layers, thereby exposing a portion of said substrate surface; etching said exposed portion of said substrate to a level below said surface of said substrate; growing a field oxide region on said etched portion of said substrate; removing said layers, thereby forming an indentation within said field oxide region; and substantially eliminating said indentation, wherein said indentation is eliminated by: filling said indentation with a conformal film; planarizing said conformal film; and oxidizing said conformal film.
Claim 2
Independent Claim 111 words
A method for forming an isolation device comprising the following steps of: providing a semiconductor substrate having a surface; forming a plurality of layers on the surface of said semiconductor substrate; patterning and etching said layers, thereby exposing a portion of said substrate surface; etching said exposed portion of said substrate to a level below said surface of said substrate; growing a field oxide region on said etched portion of said substrate; removing said layers, thereby forming an indentation within said field oxide region; and substantially eliminating said indentation, wherein said indentation is eliminated by: filling said indentation with a conformal film; planarizing said conformal film; and oxidizing said conformal film.
Claim 3
Dependent Claim 12 words
The method according to claim 1, wherein said conformal film comprises polysilicon.
Claim 4
Dependent Claim 11 words
The method according to claim 2, wherein said planarizing comprises etching.
Claim 5
Dependent Claim 15 words
The method according to claim 3, wherein said substrate is etched 500Å below said surface.
Claim 6
Dependent Claim 34 words
The method according to claim 1, further comprising the steps of: depositing a nitride film on said etched portion of said substrate surface; and anisotropically etching said nitride film, thereby forming a nitride spacer.
Claim 7
Dependent Claim 17 words
The method according to claim 5, wherein said nitride spacer is in the approximate range of 250Å-500Å.
Claim 8
Dependent Claim 108 words
A process useful for isolating active areas of semiconductor devices, comprising the following steps of: forming at least a pad oxide layer, a polysilicon layer, and a nitride layer superjacent a substrate; patterning and etching said layers and said substrate, thereby forming a recess in said substrate; forming a nitride spacer within said recess; growing field oxide region in said recess, said field oxide region having a periphery; removing said layers, said removal causing an indentation to form within said periphery of said field oxide region; disposing polysilicon within said indentation; etching said polysilicon to a level essentially planar with said field oxide region; and oxidizing said polysilicon.
Claim 9
Dependent Claim 108 words
A process useful for isolating active areas of semiconductor devices, comprising the following steps of: forming at least a pad oxide layer, a polysilicon layer, and a nitride layer superjacent a substrate; patterning and etching said layers and said substrate, thereby forming a recess in said substrate; forming a nitride spacer within said recess; growing field oxide region in said recess, said field oxide region having a periphery; removing said layers, said removal causing an indentation to form within said periphery of said field oxide region; disposing polysilicon within said indentation; etching said polysilicon to a level essentially planar with said field oxide region; and oxidizing said polysilicon.
Claim 10
Dependent Claim 16 words
The process according to claim 7, further comprising the step of: removing said pad oxide layer.
Claim 11
Dependent Claim 23 words
The process according to claim 8, wherein said nitride spacer is formed by: depositing a nitride film; and anisotropically etching said nitride film.
Claim 12
Dependent Claim 16 words
The process according to claim 9, wherein said anisotropic etch is performed in a plasma environment.
Claim 13
Dependent Claim 13 words
The process according to claim 10, wherein said nitride film is conformally deposited.
Claim 14
Dependent Claim 17 words
The process according to claim 11, wherein said nitride spacer is in the approximate range of 250Å-500Å.
Claim 15
Dependent Claim 18 words
The process according to claim 12, wherein said semiconductor devices have an active area-field pitch below 0.9 μm.
Claim 16
Dependent Claim 85 words
A process for fabricating a recessed field oxide area, comprising the following steps of: disposing successive layers of pad oxide/nitride/oxide/polysilicon/nitride on a substrate; anisotropically etching said layers and said substrate, thereby forming a recess in said substrate; oxidizing the resulting exposed portion of said substrate, thereby forming a field oxide region; removing said nitride/oxide/polysilicon/nitride layers, thereby causing irregularities in said field oxide region; depositing a polysilicon film superjacent said substrate; dry etching said polysilicon film; oxidizing said polysilicon film; and stripping said pad oxide layer.
Claim 17
Dependent Claim 85 words
A process for fabricating a recessed field oxide area, comprising the following steps of: disposing successive layers of pad oxide/nitride/oxide/polysilicon/nitride on a substrate; anisotropically etching said layers and said substrate, thereby forming a recess in said substrate; oxidizing the resulting exposed portion of said substrate, thereby forming a field oxide region; removing said nitride/oxide/polysilicon/nitride layers, thereby causing irregularities in said field oxide region; depositing a polysilicon film superjacent said substrate; dry etching said polysilicon film; oxidizing said polysilicon film; and stripping said pad oxide layer.
Claim 18
Dependent Claim 20 words
The process according to claim 14, wherein said deposited polysilicon film fills in any irregularities in said field oxide region.
Claim 19
Dependent Claim 16 words
The process according to claim 15, wherein said substrate is etched 500Å to form said recess.
Claim 20
Dependent Claim 17 words
The process according to claim 15, wherein said irregularities comprise at least one of corners and indentations.
Claim 21
Dependent Claim 18 words
The process according to claim 14, wherein a nitride spacer is formed in said recess of said substrate.
Claim 22
Dependent Claim 16 words
The process according to claim 18, wherein said nitride spacer is consumed during said substrate oxidation.
Claim 23
Dependent Claim 17 words
The process according to claim 18, wherein said nitride spacer is in the approximate range of 250Å-500Å.

References Cited (Backward Citations)

GB2101399A Cited
EP0120614A1 Cited
JPS60145638A Cited
US4541167A Cited
JPH04150030A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-02-27 1998-08-29 1999-02-28 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-02-27 2002-08-29 2003-02-28 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-02-27 2006-08-29 2007-02-28 $7700.00 Window Closed / Lapsed

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