Coherent copyback protocol for multi-level cache memory systems

Claim 1

A computer system having a plurality of cache memories organized in a hierarchy comprising: a processor; a first level cache memory within the processor, wherein the first level cache memory is a highest level cache memory; a second level cache memory coupled to the first level cache memory, wherein the second level cache memory is a second-highest level cache memory; a third level cache memory coupled to the second level cache memory, wherein the third level cache memory is a third-highest level cache memory; a main memory which acts as a fourth level cache memory, wherein the main memory is a fourth-highest level cache memory; and a shared memory bus coupling the third level cache memory to the fourth level cache memory; wherein any one cache memory of the first, second, third, or fourth level cache memories may include a line of data in any one of a plurality of states including: a Modified state in which the line of data is exclusively available in only the one cache memory and has been modified; a Shared state in which the line of data may exist in the one cache memory and any other cache memory at a same time; and an Invalid state in which the line of data is unavailable; and wherein any one cache memory of the second, third, or fourth level cache memories may include a line of data in a Latest state in which the line of data is a most recent copy of Modified data, and in which the line of data in all higher-level cache memories is in the Invalid state and the line of data in all lower-level cache memories is in the Modified state.