US5214765A
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Method and apparatus for executing floating point instructions utilizing complimentary floating point pipeline and multi-level caches
Assignee: Sun Microsystems Inc
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Filing: 1992-07-02
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Granted: 1993-05-25
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Expires: 2012-07-02
Abstract
Abstract A primary, a secondary, and a tertiary cache, and a floating point pipeline having optimized complimentary characteristics are provided to a computer system for executing floating point instructions. The primary cache is direct mapped and having n 1 cache lines, each having a cache line size of m 1 floating point data word(s) and an access time of t 1 clock cycle(s), where m 1 and t 1 are both small integer greater than or equal to 1. The secondary cache is fully associative having n 2 cache lines, each having a cache line size of m 2 floating point data words and an access time of t 2 clock cycles, where n 2 is a small integer, m 2 is greater than m 1 , and t 2 is a small integer greater than t 1 . The tertiary cache has n 3 cache lines, each having a cache line size of m 3 floating point data words and an access time of t 3 clock cycles, where m 3 is greater than m 2 and t 3 is a small integer greater than t 2 . The tertiary cache may be direct mapped or set associative. The a floating point pipeline has a fetching phase, a decoding phase, d delay phases requiring at least t 1 +t 2 clock cycles, and at least one floating point execution phase.
Inventors
- 👤 Eric H. Jensen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 17:55
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0893; G06F12/0897
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
319 words
In a pipeline computer system comprising a plurality of floating point instructions, a method for executing floating point instructions, said method comprising the steps of: a) storing a first plurality of floating point data in a primary direct mapped cache, said primary cache comprising n 1 cache lines, each having a first cache line size of m 1 floating point data word(s) and a first access time of t 1 clock cycle(s), where m 1 and t 1 are both small integers greater than or equal to 1; b) storing a second plurality of floating point data in a secondary fully associative cache, said secondary cache comprising n 2 cache lines, each having a second cache line size of m 2 floating point data words and a second access time of t 2 clock cycles, where n 2 is a small integer, m 2 is greater than m 1 , and t 2 is a small integer greater than t 1 . c) storing a third plurality of floating point data in a tertiary cache, said tertiary cache comprising n 3 cache lines, each having a third cache line size of m 3 floating point data words and a third access time of t 3 clock cycles, where m 3 is greater than m 2 and t 3 is a small integer greater than t 2 ; d) executing at least one fetching and one decoding floating point phase to fetch and decode a floating point instruction, said floating point instruction being preceded by a floating point data loading instruction to load at least one floating point data word from a selected one of said primary, secondary and tertiary cache; e) executing d floating point delay phases, said d floating point delay phases requiring at least t 1 +t 2 clock cycles; and f) executing at least one floating point execution phase to execute said decoded floating point instruction.
Claim 2
Dependent Claim
319 words
In a pipeline computer system comprising a plurality of floating point instructions, a method for executing floating point instructions, said method comprising the steps of: a) storing a first plurality of floating point data in a primary direct mapped cache, said primary cache comprising n 1 cache lines, each having a first cache line size of m 1 floating point data word(s) and a first access time of t 1 clock cycle(s), where m 1 and t 1 are both small integers greater than or equal to 1; b) storing a second plurality of floating point data in a secondary fully associative cache, said secondary cache comprising n 2 cache lines, each having a second cache line size of m 2 floating point data words and a second access time of t 2 clock cycles, where n 2 is a small integer, m 2 is greater than m 1 , and t 2 is a small integer greater than t 1 . c) storing a third plurality of floating point data in a tertiary cache, said tertiary cache comprising n 3 cache lines, each having a third cache line size of m 3 floating point data words and a third access time of t 3 clock cycles, where m 3 is greater than m 2 and t 3 is a small integer greater than t 2 ; d) executing at least one fetching and one decoding floating point phase to fetch and decode a floating point instruction, said floating point instruction being preceded by a floating point data loading instruction to load at least one floating point data word from a selected one of said primary, secondary and tertiary cache; e) executing d floating point delay phases, said d floating point delay phases requiring at least t 1 +t 2 clock cycles; and f) executing at least one floating point execution phase to execute said decoded floating point instruction.
Claim 3
Dependent Claim
30 words
The method as set forth in claim 1, wherein, m 1 and t 1 both equal 1; m 2 equals 64 and t 2 equals 2; and d equals 3.
Claim 4
Dependent Claim
13 words
The method as set forth in claim 2, wherein n 2 equals 16.
Claim 5
Dependent Claim
341 words
In a pipelined computer system comprising a plurality of floating point instructions, an apparatus for executing floating point instructions, said apparatus comprising: a) a primary direct mapped cache for storing a first plurality of floating point data in a primary direct mapped cache, said primary cache comprising n 1 cache lines, each having a first cache line size of m 1 floating point data word(s) and a first access time of t 1 clock cycle(s), where m 1 and t 1 are both small integers greater than or equal to 1; b) a secondary fully associative cache for storing a second plurality of floating point data in a secondary fully associative cache, said secondary cache comprising n 2 cache lines, each having a second cache line size of m 2 floating point data words and a second access time of t 2 clock cycles, where n 2 is a small integer, m 2 is greater than m 1 and t 2 is a small integer greater than t 1 ; c) a tertiary cache for storing a third plurality of floating point data in a tertiary cache, said tertiary cache comprising n 3 cache lines, each having a third cache line size of m 3 floating point data words and a third access time of t 3 clock cycles, where m 3 is greater than m 2 and t 3 is a small integer greater than t 2 ; and d) a floating point pipeline coupled to said primary, secondary, and tertiary caches for executing at least one fetching and one decoding floating point phase to fetch and decode a floating point instruction, d floating point delay phases, said d floating point delay phases requiring at least t 1 +t 2 clock cycles, and at least one floating point execution phase to execute said decoded floating point instruction, said floating point instruction being preceded by a floating point data loading instruction to load at least one floating point data word from a selected one of said primary, secondary and tertiary cache.
Claim 6
Dependent Claim
341 words
In a pipelined computer system comprising a plurality of floating point instructions, an apparatus for executing floating point instructions, said apparatus comprising: a) a primary direct mapped cache for storing a first plurality of floating point data in a primary direct mapped cache, said primary cache comprising n 1 cache lines, each having a first cache line size of m 1 floating point data word(s) and a first access time of t 1 clock cycle(s), where m 1 and t 1 are both small integers greater than or equal to 1; b) a secondary fully associative cache for storing a second plurality of floating point data in a secondary fully associative cache, said secondary cache comprising n 2 cache lines, each having a second cache line size of m 2 floating point data words and a second access time of t 2 clock cycles, where n 2 is a small integer, m 2 is greater than m 1 and t 2 is a small integer greater than t 1 ; c) a tertiary cache for storing a third plurality of floating point data in a tertiary cache, said tertiary cache comprising n 3 cache lines, each having a third cache line size of m 3 floating point data words and a third access time of t 3 clock cycles, where m 3 is greater than m 2 and t 3 is a small integer greater than t 2 ; and d) a floating point pipeline coupled to said primary, secondary, and tertiary caches for executing at least one fetching and one decoding floating point phase to fetch and decode a floating point instruction, d floating point delay phases, said d floating point delay phases requiring at least t 1 +t 2 clock cycles, and at least one floating point execution phase to execute said decoded floating point instruction, said floating point instruction being preceded by a floating point data loading instruction to load at least one floating point data word from a selected one of said primary, secondary and tertiary cache.
Claim 7
Dependent Claim
31 words
The apparatus as set forth in claim 4, wherein, m 1 and t 1 are both equal 1; m 2 equals 64 and t 2 equals 2; and d equals 3.
Claim 8
Dependent Claim
13 words
The apparatus as set forth in claim 5, wherein n 2 equals 16.
Claim 9
Dependent Claim
323 words
A computer system comprising: a) a primary direct mapped cache for storing a first plurality of floating point data in a primary direct mapped cache, said primary cache comprising n 1 cache lines, each having a first cache line size of m 1 floating point data word(s) and a first access time of t 1 clock cycle(s), where m 1 and t 1 are both small integers greater than or equal to 1; b) a secondary fully associative cache for storing a second plurality of floating point data in a secondary fully associative cache, said secondary cache comprising n 2 cache lines, each having a second cache line size of m 2 floating point data words and a second access time of t 2 clock cycles, where n 2 is a small integer, m 2 is greater than m 1 and t 2 is a small integer greater than t 1 ; c) a tertiary cache for storing a third plurality of floating point data in a tertiary cache, said tertiary cache comprising n 3 cache lines, each having a third cache line size of m 3 floating point data words and a third access time of t 3 clock cycles, where m 3 is greater than m 2 and t 3 is a small integer greater than t 2 ; and d) a floating point pipeline coupled to said primary, secondary, and tertiary caches for executing at least one fetching and one decoding floating point phase to fetch and decode a floating point instruction, d floating point delay phases, said d floating point delay phases requiring at least t 1 +t 2 clock cycles, and at least one floating point execution phase to execute said decoded floating point instruction, said floating point instruction being preceded by a floating point data loading instruction to load at least one floating point data word from a selected one of said primary, secondary and tertiary cache.
Claim 10
Dependent Claim
323 words
A computer system comprising: a) a primary direct mapped cache for storing a first plurality of floating point data in a primary direct mapped cache, said primary cache comprising n 1 cache lines, each having a first cache line size of m 1 floating point data word(s) and a first access time of t 1 clock cycle(s), where m 1 and t 1 are both small integers greater than or equal to 1; b) a secondary fully associative cache for storing a second plurality of floating point data in a secondary fully associative cache, said secondary cache comprising n 2 cache lines, each having a second cache line size of m 2 floating point data words and a second access time of t 2 clock cycles, where n 2 is a small integer, m 2 is greater than m 1 and t 2 is a small integer greater than t 1 ; c) a tertiary cache for storing a third plurality of floating point data in a tertiary cache, said tertiary cache comprising n 3 cache lines, each having a third cache line size of m 3 floating point data words and a third access time of t 3 clock cycles, where m 3 is greater than m 2 and t 3 is a small integer greater than t 2 ; and d) a floating point pipeline coupled to said primary, secondary, and tertiary caches for executing at least one fetching and one decoding floating point phase to fetch and decode a floating point instruction, d floating point delay phases, said d floating point delay phases requiring at least t 1 +t 2 clock cycles, and at least one floating point execution phase to execute said decoded floating point instruction, said floating point instruction being preceded by a floating point data loading instruction to load at least one floating point data word from a selected one of said primary, secondary and tertiary cache.
Claim 11
Dependent Claim
32 words
The computer system as set forth in claim 7, wherein, m 1 and t 1 are both equal 1; m 2 equals 64 and t 2 equals 2; and d equals 3.
Claim 12
Dependent Claim
14 words
The computer system as set forth in claim 8, wherein n 2 equals 16.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-24 | 1996-11-23 | 1997-05-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-24 | 2000-11-23 | 2001-05-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-24 | 2004-11-23 | 2005-05-25 | $7700.00 | Window Closed / Lapsed |