Pseudo set-associative memory cacheing arrangement

Claim 2

A data processing system comprising a central processor (20) and a hierarchical memory system comprising at least one main large memory (21) having a relatively long access time and a pseudo set-associative cache memory comprising a plurality of cache memory banks (A,B,C,D) each comprising a plurality of addressable locations defined by cache addresses comprising n least significant bits of a main memory address and means (A,B,C,D) for mapping each memory bank to a respective area of main memory.

Claim 3

A data processing system as defined in claim 1 wherein the mapping means comprises a plurality of cache select circuits (A,B,C,D) each one associated with a respective one of the cache memory banks (A,B,C,D) and each one being responsive to m most significant bits of a main memory address and predetermined control signals for asserting an enable signal to its respective cache memory bank when said m most significant bits correspond to a predetermined range of addresses in main memory.

Claim 4

A data processing system as defined in claim 2 wherein each cache select circuit (A,B,C,D) comprises means (39) for storing an asserted enable signal.

Claim 5

A data processing system as defined in claim 3 wherein an enable signal remains asserted until it becomes unasserted in a subsequent memory cycle.

Claim 6

A data processing system as defined in claim 4 wherein a newly asserted enable signal is generated only during a miss cache memory cycle.

Claim 7

A data processing system as defined in claim 5 wherein the memory address ranges defined by the various cache select circuits (A,B,C,D) map to mutually exclusive areas of main memory.

Claim 8

A data processing system as defined in claim 6 wherein each cache select circuit (A,B,C,D) further comprises a first register (33) for storing m bits corresponding to the start address of a memory range, a second register (34) for storing m bits corresponding to the end address of the memory range, comparator means (30,31) for providing an output signal during a memory addressing cycle of the processor (20) if the m bits of the memory address from the processor correspond to an address which is less than or equal to the end address stored in the second register (34) and is greater or equal to the start address stored in the first register (33) and gating means (38) for storing said output signal into the storage means (39) under control of predetermined signals.

Claim 9

A data processing system as defined in claim 7 wherein the storage means (39) for storing an asserted cache select signal is a flip-flop.

Claim 10

A data processing system as defined in claim 8 wherein each cache select circuit (A,B,C,D) still further comprises, circuit means (35) for loading said start and end addresses in the first and second registers under control of the processor.

Claim 11

A pseudo set-associative memory cacheing arrangement for use in conjunction with a processor (20) interfacing to a main memory (21) and adapted to support a cache memory, the arrangement comprising a plurality of cache memory banks (A,B,C,D) each comprising a respective number of addressable locations defined by cache addresses comprising n least significant bits of a main memory address and each being responsive to a cache address, a read signal from the processor and a cache select signal for outputting the data at the addressed location to the data bus (22) of the processor (20), a plurality of cache select circuits each one associated with a respective one of the cache memory banks (A,B,C,D) and each one being responsive to m most significant bits of a main memory address and predetermined control signals for asserting a cache bank select signal to its associated cache memory bank when said m most significant bits correspond to a predetermined main memory range of addresses.

Claim 12

A pseudo set-associative memory cacheing arrangement for use in conjunction with a processor (20) interfacing to a main memory (21) and adapted to support a cache memory, the arrangement comprising a plurality of cache memory banks (A,B,C,D) each comprising a respective number of addressable locations defined by cache addresses comprising n least significant bits of a main memory address and each being responsive to a cache address, a read signal from the processor and a cache select signal for outputting the data at the addressed location to the data bus (22) of the processor (20), a plurality of cache select circuits each one associated with a respective one of the cache memory banks (A,B,C,D) and each one being responsive to m most significant bits of a main memory address and predetermined control signals for asserting a cache bank select signal to its associated cache memory bank when said m most significant bits correspond to a predetermined main memory range of addresses.

Claim 13

A pseudo set-associative memory cacheing arrangement as defined in claim 10 wherein each select circuit (A,B,C,D) comprises storage means (39) for storing an asserted cache select signal until it becomes unasserted during a subsequent memory cycle.

Claim 14

A pseudo set-associative memory cacheing arrangement as defined in claim 11 wherein a newly asserted enable signal is generated only during a miss cache memory cycle.

Claim 15

A pseudo set-associative memory cacheing arrangement as defined in claim 12 wherein each cache select circuit (A,B,C,D) maps unto a respective range of memory locations of main memory (21).

Claim 16

A pseudo set-associative memory cacheing arrangement as defined in claim 13 wherein the memory address ranges defined by the various cache select circuits (A,B,C,D) are non-overlapping.

Claim 17

A pseudo set-associative memory cacheing arrangement as defined in claim 14 wherein each cache select circuit (A,B,C,D) further comprises a first register (33) for storing m bits corresponding to the start address of a memory range, a second register (34) for storing m bits corresponding to the end address of the memory range, comparator means (30,31) for providing an output signal during a memory addressing cycle of the processor if the m bits of the memory address from the processor (20) correspond to an address which is less than or equal to the end address stored in the second register (34) and is greater or equal to the start address stored in the first register (33) and gating means (38) for storing said output signal into the storage means (39) under control of predetermined signals.

Claim 18

A pseudo set-associative memory cacheing arrangement as defined in claim 15 wherein the storage means (39) for storing an asserted cache select signal is a flip-­flop.

Claim 19

A pseudo set-associative memory cacheing arrangement as defined in claim 16 wherein each cache select circuit (A,B,C,D) still further comprises, circuit means (35) for loading said start and end addresses in the first and second registers under control of the processor.

Claim 22

A method of cacheing instructions in a data processing system as defined in claim 18 wherein the mapping is achieved by providing a plurality of cache select circuits (A,B,C,D) each one associated with a respective one of the cache memory banks (A,B,C,D) and each one being responsive to m most significant bits of a main memory address and predetermined control signals for asserting an enable signal to its respective cache memory bank when said m most significant bits correspond to a predetermined main memory range of addresses.

Claim 23

A method of cacheing instruction data in a data processing system as defined in claim 19 and comprising the further step of storing an asserted enable signal from a cache select circuit (A,B,C,D) to its associated cache memory bank (A,B,C,D) until it becomes unasserted during a subsequent memory cycle.

Claim 24

A method of cacheing instruction data in a data processing system as defined in claim 20 wherein a newly asserted enable signal is generated only during a miss cache memory cycle.

Claim 25

A method of cacheing instruction data in a data processing system as defined in claim 21 wherein the memory address ranges defined by the various cache select circuits (A,B,C,D) are non-overlapping.