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US5287484A
Expired / Lapsed
US
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Multi-processor system for invalidating hierarchical cache
Assignee: Hitachi Ltd
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Filing: 1992-11-13
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Granted: 1994-02-15
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Expires: 2012-11-13
Abstract
Abstract A non-shared system with respect to an outside and an inside cache in a multi-processor system has multi-layer hierarchical cache. An invalidation address on a main memory address bus 31 in company with the rewriting of a main memory 30 is transmitted via a first and a second path 35, 36 to inside caches 11,21 so as to invalidate these inside caches 11, 21. The invalidation address is transmitted to the outside caches 12, 22 via the bidirectional connections between the main memory address bus 31 and outside caches 12, 22 so as to invalidate these outside caches 12, 22. It is extremely improbable for the address of access for writing to the transmitted to the main memory address bus 31 because the outside caches 12, 22 are operated in either copy back or write once system. As a result, even though the invalidation address is transmitted to the outside caches 12, 22 via the bidirectional connections between the main memory address bus 31 and the outside caches 12, 22, it is extremely improbably for the address of access for writing to conflict with a signal on the bidirectional connection.
Inventors
- 👤 Osamu Nishii
- 👤 Kunio Uchiyama
- 👤 Hirokazu Aoki
- 👤 Takashi Kikuchi
- 👤 Yasuhiko Saigou
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 14:02
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0811; G06F12/0893; G06F12/0897
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
571 words
A multi-processor system comprising: (1) a first processor for generating a first address to a first processor address line; (2) a first inside cache memory to be accessed by said first processor in accordance with the first address on said first processor address line; (3) a first outside cache memory to be accessed by said first processor in accordance with the first address on a first cache address line between said first inside cache memory and said first outside cache memory; (4) a second processor for generating a second address to a second processor address line; (5) a second inside cache memory to be accessed by said second processor in accordance with the second address on said second processor address line; (6) a second outside cache memory to be accessed by said second processor in accordance with the second address on said second cache address line between said second inside cache memory and said second outside cache memory; (7) an address bus connected to said first and second outside cache memories by bidirectional first and second connections, respectively, and to which the first address transmitted from said first processor can be therein received via said first outside cache memory and the second address transmitted from said second processor can be therein received via said second outside cache memory; (8) a data bus for transmitting data and connected to said first outside cache memory for communicating the data to said first processor and said first inside cache memory and connected to said second outside cache memory for communicating the data to said second processor and said second inside cache memory; (9) memory means connected to said address bus and said data bus, said memory means being accessed by said first address which is transmitted from said first processor via said first processor address line, said first inside cache memory, said first cache address line, said first outside cache memory and said bidirectional first connection to said address bus and accessed by said second address which is transmitted from said second processor via said second processor address line, said second inside cache memory, said second cache address line, said second outside cache memory and said bidirectional second connection to said address bus; and (10) first and second paths for respectively directly connecting said address bus with said first inside cache memory and said second inside cache memory for direct reception of addresses at the inside cache memories form the address bus by circumventing said first outside cache memory and said second outside cache memory, wherein said first inside cache memory and said second inside cache memory operate in a write through system, wherein said first outside cache memory and said second outside cache memory operate in at least one of a copy back system in which no address of write access is transmitted to said address bus at the time of cache hit and a write once system in which no address of write access is transmitted to said address bus when data of a specific address is modified more than once, and wherein an invalidation address on said address bus which is generated in accompaniment with rewriting of said memory means is transmitted to said first cache inside memory, said second inside cache memory, said first outside cache memory and said second outside cache memory through said first path, said second path, said bidirectional first connection and said bidirectional second connection, respectively.
Claim 2
Dependent Claim
571 words
A multi-processor system comprising: (1) a first processor for generating a first address to a first processor address line; (2) a first inside cache memory to be accessed by said first processor in accordance with the first address on said first processor address line; (3) a first outside cache memory to be accessed by said first processor in accordance with the first address on a first cache address line between said first inside cache memory and said first outside cache memory; (4) a second processor for generating a second address to a second processor address line; (5) a second inside cache memory to be accessed by said second processor in accordance with the second address on said second processor address line; (6) a second outside cache memory to be accessed by said second processor in accordance with the second address on said second cache address line between said second inside cache memory and said second outside cache memory; (7) an address bus connected to said first and second outside cache memories by bidirectional first and second connections, respectively, and to which the first address transmitted from said first processor can be therein received via said first outside cache memory and the second address transmitted from said second processor can be therein received via said second outside cache memory; (8) a data bus for transmitting data and connected to said first outside cache memory for communicating the data to said first processor and said first inside cache memory and connected to said second outside cache memory for communicating the data to said second processor and said second inside cache memory; (9) memory means connected to said address bus and said data bus, said memory means being accessed by said first address which is transmitted from said first processor via said first processor address line, said first inside cache memory, said first cache address line, said first outside cache memory and said bidirectional first connection to said address bus and accessed by said second address which is transmitted from said second processor via said second processor address line, said second inside cache memory, said second cache address line, said second outside cache memory and said bidirectional second connection to said address bus; and (10) first and second paths for respectively directly connecting said address bus with said first inside cache memory and said second inside cache memory for direct reception of addresses at the inside cache memories form the address bus by circumventing said first outside cache memory and said second outside cache memory, wherein said first inside cache memory and said second inside cache memory operate in a write through system, wherein said first outside cache memory and said second outside cache memory operate in at least one of a copy back system in which no address of write access is transmitted to said address bus at the time of cache hit and a write once system in which no address of write access is transmitted to said address bus when data of a specific address is modified more than once, and wherein an invalidation address on said address bus which is generated in accompaniment with rewriting of said memory means is transmitted to said first cache inside memory, said second inside cache memory, said first outside cache memory and said second outside cache memory through said first path, said second path, said bidirectional first connection and said bidirectional second connection, respectively.
Claim 3
Dependent Claim
100 words
The multi-processor system as claimed in claim 1, further comprising an input/output device connected to said address bus and said data bus, wherein addresses and data are transferred via said address bus and said data bus, respectively, from said input/output device to said memory means, and wherein an address being transferred on said address bus is supplied via said first and second paths to said first and second inside caches, respectively and supplied via said first and second connections to said first and said second outside caches, whereby any data held in said caches related to said address is invalidated.
Claim 4
Dependent Claim
15 words
The multi-processor system claimed in claim 2, wherein said memory means is a main memory.
Claim 5
Dependent Claim
177 words
The multi-processor system as claimed in claim 1, wherein said first inside cache has a dual port RAM comprising a first address array capable of being accessed in parallel by means of the first address from said first processor and the addresses on said address bus via said first path, wherein said second inside cache has a dual port RAM comprising a second address array capable of being accessed in parallel by means of the second address from said second processor and the addresses on said address bus via said second path, wherein said first outside cache has a dual port RAM comprising a third address array capable of being accessed in parallel by means of the first address from said first processor and the addresses on said address bus via said first connection, and wherein said second outside cache has a dual port RAM comprising a fourth address array capable of being accessed in parallel by means of the second address from said second processor and the addresses on said address bus via said second connection.
Claim 6
Dependent Claim
178 words
The multi-processor system as claimed in claim 2, wherein said first inside cache has a dual port RAM comprising a first address array capable of being accessed in parallel by means of the first address from said first processor and the addresses on said address bus via said first path, and wherein said second inside cache has a dual port RAM comprising a second address array capable of being accessed in parallel by means of the second address from said second processor and the addresses on said address bus via said second path, wherein said first outside cache has a dual port RAM comprising a third address array capable of being accessed in parallel by means of the first address from said first processor and the addresses on said address bus via said first connection, and wherein said second outside cache has a dual port RAM comprising a fourth address array capable of being accessed in parallel by means of the second address from said second processor and the addresses on said address bus via said second connection.
Claim 7
Dependent Claim
178 words
The multi-processor system as claim in claim 3, wherein said first inside cache has a dual port RAM comprising a first address array capable of being accessed in parallel by means of th e first address from said first processor and the addresses on said address bus via said first path, wherein said second outside cache has a dual port RAM comprising a second address array capable of being accessed in parallel by means of the second address from said second processor and the addresses on said address bus via said second path, wherein said first outside cache has a dual port RAM comprising a third address array capable of being accessed in parallel by means of the first address from said first processor and the addresses on said address bus via said first connection, and wherein said second outside cache has a dual port RAM comprising a fourth address array capable of being accessed in parallel by means of the second address from said second processor and the addresses on said address bus via said second connection.
Claim 8
Dependent Claim
133 words
The multi-processor system as claimed in claim 1, wherein said first and second outside cache memories include means for monitoring the addresses on said address bus for demanding a write access on said address bus via said first and second connections, when at least one of said first and second outside cache memories receives a hit of a one of said addresses and when the data related to said one address thus hit is not updated only in said hit cache, said hit cache including means for invalidating the data related to the one address and for selectively setting a bit instruction of the writing of the data to the hit cache and the memory means in a write once system at a time of the write access related to said one address.
Claim 9
Dependent Claim
16 words
The multi-processor system as claimed in claim 7, wherein said memory means is a main memory.
Claim 10
Dependent Claim
177 words
The multi-processor system as claimed in claim 7, wherein said first inside cache has a dual port RAM comprising a first address array capable of being accessed in parallel by means of the first address from said first processor and the addresses on said address bus via said first path, wherein said second inside cache has a dual port RAM comprising a second address array capable of being accessed in parallel by means of the second address from said second processor and the addresses on said address bus via said second path, wherein said first outside cache has a dual port RAM comprising a third address array capable of being accessed in parallel by means of the first address from said first processor and the addresses on said address bus via said first connection, and wherein said second outside cache has a dual port RAM comprising a fourth address array capable of being accessed in parallel by means of the second address from said second processor and the addresses on said address bus via said second connection.
Claim 11
Dependent Claim
177 words
The multi-processor system as claimed in claim 8, wherein said first inside cache has a dual port RAM comprising a first address array capable of being accessed in parallel by means of the first address from said first processor and the addresses on said address bus via said first path, wherein said second inside cache has a dual port RAM comprising a second address array capable of being accessed in parallel by means of the second address from said second processor and the addresses on said address bus via said second path, wherein said first outside cache has a dual port RAM comprising a third address array capable of being accessed in parallel by means of the first address from said first processor and the addresses on said address bus via said first connection, and wherein said second outside cache has a dual port RAM comprising a fourth address array capable of being accessed in parallel by means of the second address from said second processor and the addresses on said address bus via said second connection.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-14 | 1997-08-16 | 1998-02-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-14 | 2001-08-16 | 2002-02-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-14 | 2005-08-16 | 2006-02-15 | $7700.00 | Window Closed / Lapsed |