US4939641A
Expired / Lapsed
US
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Multi-processor system with cache memories
Assignee: LG Electronics Inc
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Filing: 1988-06-30
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Granted: 1990-07-03
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Expires: 2008-06-30
Abstract
Abstract A system is described wherein a CPU, a main memory means and a bus means are provided. Cache memory means is employed to couple the CPU to the bus means and is further provided with means to indicate the status of a data unit stored within the cache memory means. One status indication tells whether the contents of a storage position have been modified since those contents were received from main memory and another indicates whether the contents of the storage position may be present elsewhere memory means. Control means are provided to assure that when a data unit from a CPU is received and stored in the CPU's associated cache memory means, which data unit is indicated as being also stored in a cache memory means associated with another CPU, such CPU data unit is also written into main memory means. During that process, other cache memory means monitor the bus means and update its corresponding data unit. Bus monitor means are provided and monitor all writes to main memory and reads from main memory to aid in the assurance of system-wide data integrity.
Inventors
- 👤 Martin J. Schwartz
- 👤 Robert D. Becker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 15:55
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831; G06F12/0833
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
212 words
A data processing system including one or more central processing units, main memory means, and bus means, for each central processing unit the invention comprising: cache memory means coupled between the central processing unit and said bus means; bus monitor means associated with said cache memory means and coupled to said bus means for detecting on said bus means an address associated with a data unit transferred from said main memory means to a bus connection requesting the data unit; means coupled to said cache memory means and to said bus means for determining if data having the same address as said transferred data unit is present in said cache memory means and, if present, for asserting a hold signal on said bus means, the assertion of the hold signal indicating at least to the bus connection requesting the data unit that another data unit may be transmitted over said bus means; and means for detecting whether data corresponding to the address of said transferred data unit and determined to be stored in said cache memory means may be different in content from said transferred data unit and, if so, transmitting said data from said cache memory means to said bus means for reception by the bus connection requesting the data unit.
Claim 2
Dependent Claim
212 words
A data processing system including one or more central processing units, main memory means, and bus means, for each central processing unit the invention comprising: cache memory means coupled between the central processing unit and said bus means; bus monitor means associated with said cache memory means and coupled to said bus means for detecting on said bus means an address associated with a data unit transferred from said main memory means to a bus connection requesting the data unit; means coupled to said cache memory means and to said bus means for determining if data having the same address as said transferred data unit is present in said cache memory means and, if present, for asserting a hold signal on said bus means, the assertion of the hold signal indicating at least to the bus connection requesting the data unit that another data unit may be transmitted over said bus means; and means for detecting whether data corresponding to the address of said transferred data unit and determined to be stored in said cache memory means may be different in content from said transferred data unit and, if so, transmitting said data from said cache memory means to said bus means for reception by the bus connection requesting the data unit.
Claim 3
Dependent Claim
52 words
The invention as defined in claim 1 wherein said bus connection requesting the data unit, in response to sensing the assertion of said hold signal, maintains an interaction with said bus means so that the bus connection requesting the data unit may receive said different content data from said cache memory means.
Claim 4
Dependent Claim
82 words
The invention as defined in claim 2 and further comprising: a multi-data unit transfer register; and means coupled to said bus means and responsive thereto for detecting a multi-data unit read onto said bus means from said main memory means and for determining if any said data unit is present in said cache memory means; said detecting means further including means for recording an indication of such presence in said multi-data unit transfer register and causing said hold line to be asserted.
Claim 5
Dependent Claim
48 words
The invention as defined in claim 3 and further including means for transferring from said cache memory means to the recipient of said multi-data unit transfer each said data unit indicated by said multi-data unit transfer register as being present and which is also determined to be dirty.
Claim 6
Dependent Claim
228 words
A data processing system including at least first and second central processing units, main memory means, and bus means, the invention comprising: at least first and second cache memory means respectively coupled between said first and second central processing units and said bus means; bus monitor means associated with each said cache memory means respectively and coupled to said bus means for detecting on said bus means an address associated with a data unit being read from said main memory means; means coupled to said associated cache memory means and to said bus means for determining if said corresponding to said address as detected by said bus monitor means is present in the associated cache memory means and, if said data is found to be present, for asserting a first hold signal on said bus means, the assertion of the first hold signal indicating at least to a bus connection reading the data unit that another data unit may be transmitted over said bus means; and means for detecting whether the data corresponding to said address and stored in said associated cache memory means may be different in content from that detected as being read and, if the data is determined to possibly be different in content, transmitting said data from said associated cache memory means to the bus connection reading the data unit from said main memory.
Claim 7
Dependent Claim
228 words
A data processing system including at least first and second central processing units, main memory means, and bus means, the invention comprising: at least first and second cache memory means respectively coupled between said first and second central processing units and said bus means; bus monitor means associated with each said cache memory means respectively and coupled to said bus means for detecting on said bus means an address associated with a data unit being read from said main memory means; means coupled to said associated cache memory means and to said bus means for determining if said corresponding to said address as detected by said bus monitor means is present in the associated cache memory means and, if said data is found to be present, for asserting a first hold signal on said bus means, the assertion of the first hold signal indicating at least to a bus connection reading the data unit that another data unit may be transmitted over said bus means; and means for detecting whether the data corresponding to said address and stored in said associated cache memory means may be different in content from that detected as being read and, if the data is determined to possibly be different in content, transmitting said data from said associated cache memory means to the bus connection reading the data unit from said main memory.
Claim 8
Dependent Claim
32 words
The invention as claimed in claim 5 wherein each said cache memory means comprises a cache data store, a cache tag store, a shared bit store and bus monitor cache tag store.
Claim 9
Dependent Claim
37 words
The invention as claimed in claim 6 wherein said bus monitor means captures the physical address of said data from said bus means and provides the cache address and cache tag portions thereof to said determining means.
Claim 10
Dependent Claim
51 words
The invention as claimed in claim 7 wherein said determining means compares said cache tag from said bus monitor means with a cache tag stored in its associated bus monitor cache tag store at said cache address provided by said bus monitoring means to determine if said cache tags are identical.
Claim 11
Dependent Claim
16 words
The invention as claimed in claim 8, wherein said detecting means includes a dirty bit store.
Claim 12
Dependent Claim
88 words
The invention as defined in claim 5 and further comprising for each said cache memory means: a multi-data unit transfer register; and means coupled to said bus means and responsive thereto for detecting a multi-data unit read on said bus means from said main memory means and for determining if any said data unit is present in said cache memory means; said detecting means further including means for recording an indication of such presence in said multi-data unit transfer register and causing said hold line to be asserted.
Claim 13
Dependent Claim
50 words
The invention as defined in claim 10 and further including means for transferring from said associated cache memory means to the recipient of said multi-data unit transfer each said data unit indicated by said associated multi-data unit transfer register as being present and which is also determined to be dirty.
Claim 14
Dependent Claim
50 words
The invention as defined in claim 5 wherein said determining means includes means coupled to said bus means for monitoring said bus means for sensing the presence of the assertion of a second hold signal thereon and for determining priority between the first hold signal and the second hold signal.
Claim 15
Dependent Claim
41 words
The invention as defined in claim 12 wherein said detecting means is coupled to said monitoring means and is responsive thereto for transmitting said data from said associated cache memory means in accordance with the priority determination of said monitoring means.
Claim 16
Dependent Claim
229 words
In a data processing system comprising at least one central processing unit having a cache memory coupled to a system memory through a system bus, the system bus including signal lines for conveying, during bus cycles, address information and data units associated with addresses between the system memory and other bus connections coupled to the system bus, the cache memory comprising: means for monitoring bus transactions occurring on the system bus for determining if a bus transaction occurring during a current bus cycle is an operation initiated by another bus connection that reads one or more data units from an address of the system memory; means for detecting if the address is associated with one or more data units already stored within the cache memory; and means having an input coupled to said detecting means and responsive thereto and further having an output coupled to the system bus for asserting thereon during the current bus cycle a HOLD signal line, the assertion of the HOLD signal line indicating to the bus connection initiating the read operation that at least one of the data units associated with the address is stored within the cache memory and that the cache memory will, if the data unit is determined to be marked as dirty within the cache memory, transmit the stored data unit to the bus connection during a subsequent bus cycle.
Claim 17
Dependent Claim
229 words
In a data processing system comprising at least one central processing unit having a cache memory coupled to a system memory through a system bus, the system bus including signal lines for conveying, during bus cycles, address information and data units associated with addresses between the system memory and other bus connections coupled to the system bus, the cache memory comprising: means for monitoring bus transactions occurring on the system bus for determining if a bus transaction occurring during a current bus cycle is an operation initiated by another bus connection that reads one or more data units from an address of the system memory; means for detecting if the address is associated with one or more data units already stored within the cache memory; and means having an input coupled to said detecting means and responsive thereto and further having an output coupled to the system bus for asserting thereon during the current bus cycle a HOLD signal line, the assertion of the HOLD signal line indicating to the bus connection initiating the read operation that at least one of the data units associated with the address is stored within the cache memory and that the cache memory will, if the data unit is determined to be marked as dirty within the cache memory, transmit the stored data unit to the bus connection during a subsequent bus cycle.
Claim 18
Dependent Claim
105 words
A cache memory as set forth in claim 14 and further comprising: a multi-data unit transfer register; and means coupled to the system bus and responsive thereto for detecting an occurrence of a multi-data unit read operation and for determining if any data unit read by the multi-data unit read operation is stored in the cache memory, the multi-data unit read operation detecting means further including means for recording in the multi-data unit transfer register an indication that the data unit is stored within the cache memory and further comprising means, coupled to the asserting means, for causing the HOLD signal line to be asserted.
Claim 19
Dependent Claim
64 words
A cache memory as set forth in claim 14 wherein each cache memory is coupled to an associated HOLD signal line for asserting same and wherein said monitoring means includes means for sensing an assertion of another HOLD signal line and further includes means for determining priority between an assertion of the associated HOLD signal line and an assertion of another HOLD signal line.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-07-02 | 1994-01-01 | 1994-07-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-07-02 | 1998-01-01 | 1998-07-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-07-02 | 2002-01-01 | 2002-07-03 | $7700.00 | Window Closed / Lapsed |