Semiconductor memory of xN type having error correcting circuit by parity

Claim 2

A semiconductor memory device having a memory cell array divided into a plurality of cell blocks, comprising: n memory cell blocks, for storing n-bit data, one bit of the n-bit data being stored per one memory cell block at a same address thereof; a parity memory unit for storing a parity of said n-bit data at an address corresponding to the address where said n-bit data is stored; a defective output memory unit for storing defective block data indicating a defective memory cell block among said n memory cell blocks; and a data correction circuit for correcting data in said defective memory cell block by calculating an exclusive OR of (n-1) bits of said n-bit data and the parity, the (n-1) bits being stored in said memory cell blocks at the same address except for one memory cell block indicated by said defective output memory unit, the parity being stored in said parity memory unit at the corresponding same address.

Claim 3

A semiconductor memory device according to claim 1, wherein each of said memory cell blocks and said parity memory unit have a same memory function.

Claim 4

A semiconductor memory device according to claim 1, wherein n-bit data read from said n memory cell blocks constitutes one output unit.

Claim 5

A semiconductor memory device according to claim 1, wherein the semiconductor memory device is a flash memory device.

Claim 6

A semiconductor memory device according to claim 4, wherein said defective output memory unit is made of a read-only memory.

Claim 7

A semiconductor memory device according to claim 1, wherein said data correction circuit includes exclusive OR circuit which calculates an exclusive OR of data read from normal ones of said n memory cell blocks and a parity read from said parity memory unit.

Claim 8

A semiconductor memory device according to claim 6, further comprising a parity generator for calculating a parity of data to be written.

Claim 9

A semiconductor memory device according to claim 1, wherein the semiconductor memory device is a mask ROM device.

Claim 10

A semiconductor memory device according to claim 8, wherein said parity memory unit is made of a mask ROM.

Claim 11

A semiconductor memory device according to claim 8, wherein said defective output memory unit is made of a once-programmable read-only memory.

Claim 12

A semiconductor memory device comprising: a memory cell army of a multi-bit structure having n memory cell blocks of a mask ROM structure, for storing n-bit data, one bit of the n-bit data being stored per one memory cell block at a same address per memory cell block as other bits of the n-bit data being stored; a parity cell block for storing parity data for said n-bit data at an address corresponding to the address where said n-bit data is stored, said parity data being an EOR value of said n-bit data; a defective output memory unit for storing defective block data indicating a defective one of said memory cell blocks; and a data correction circuit for correcting an error bit among said n-bit data, by calculating an exclusive OR of (n-1) bits of said n-bit data and the parity, the (n-1) bits being stored in said memory cell blocks at the same address except for one memory cell block indicated by said defective output memory unit, the parity being stored in said parity cell block at the corresponding same address, and to correct data among said n-bit data read from said memory cell blocks.

Claim 13

A semiconductor memory device comprising: a memory cell army of a multi-bit structure having n memory cell blocks of a mask ROM structure, for storing n-bit data, one bit of the n-bit data being stored per one memory cell block at a same address per memory cell block as other bits of the n-bit data being stored; a parity cell block for storing parity data for said n-bit data at an address corresponding to the address where said n-bit data is stored, said parity data being an EOR value of said n-bit data; a defective output memory unit for storing defective block data indicating a defective one of said memory cell blocks; and a data correction circuit for correcting an error bit among said n-bit data, by calculating an exclusive OR of (n-1) bits of said n-bit data and the parity, the (n-1) bits being stored in said memory cell blocks at the same address except for one memory cell block indicated by said defective output memory unit, the parity being stored in said parity cell block at the corresponding same address, and to correct data among said n-bit data read from said memory cell blocks.

Claim 14

A semiconductor memory device according to claim 11, wherein: custom data is written in said memory cell blocks at the time of manufacturing the semiconductor memory device; said parity data is written in said parity cell block at the time of manufacturing the semiconductor memory device; said defective output memory unit stores said address data of a defective memory cell block; correct data read from said memory cell blocks at an address designated by an external address signal is outputted via said data correction circuit; and said parity data selected by said external address signal is an EOR value calculated from a data train to be stored in said memory cell blocks at said address designated by said external address signal.