Word line redundancy nonvolatile semiconductor memory

Claim 1

A nonvolatile semiconductor memory comprising: a plurality of word lines in parallel formation; a plurality of bit lines in parallel formation, said bit lines being perpendicular to said word lines; a plurality of nonvolatile memory cells each of which includes: a control electrode connected to one of said word lines; a first electrode connected to one of said bit lines; and a second electrode connected to one of source lines; one or more redundant word lines; and a plurality of redundant nonvolatile memory cells each of which includes: a control electrode connected to one of said redundant word lines; a first electrode connected to one of said bit lines; and a second electrode connected to one of said source lines; if faults occur in said nonvolatile memory cells, redundant word lines are used to replace the faulty memory cell with said redundancy nonvolatile memory cell in units of a word line, wherein: said source lines are a plurality of lines arranged in one-to-one correspondence with and in parallel with said word lines or said redundant word lines; said source lines are connected to a first common source line via first switch means that have the gates thereof connected to said word lines and that selectively conduct owing to voltage applied to said word lines for reading or writing; said source lines are connected to a second common source line via second switch means that selectively conduct for erasing; and for reading or writing, a source line on which a nonvolatile memory cell concerned is connected is selectively connected to said first common source line, and the other source lines are placed in a floating state.