Semiconductor memory device having mask rom structure

Claim 2

A semiconductor memory device, comprising: a memory cell array having a plurality of memory cells and formed by a mask ROM, said memory cell array having a data area in which a plurality of stored data of n bits is stored and a parity area in which a one-bit parity code corresponding to said plurality of stored data is stored; control means for supplying said memory cell array with an address and for reading out from said memory cell array the stored data and the one-bit parity code designed by the address; parity check means for determining whether the stored data read out from said memory cell array has a bit error and for generating correction data responsive thereto; memory means for storing predetermined indicating data indicative of which of the n bits of the stored data is defective; and data correcting means for correcting the one of the n bits of the stored data indicated by the predetermined indicating data in response to the correction data generated by said parity check means.

Claim 3

A semiconductor memory device as claimed in claim 1, wherein said data correcting means comprises a correction circuit provided for each of the n bits of said data, wherein said correction circuit includes: an exclusive-OR gate having a first input terminal supplied with the correction data, a second input terminal supplied with a corresponding one of the n bits of the stored data, and an output terminal through which an output signal of said exclusive-OR gate is drawn; and selecting means for selecting one of the output signal from said exclusive-OR gate and the corresponding one of the n bits of the stored data in accordance with said defective output indicating data from said memory means.

Claim 4

A semiconductor memory device as claimed in claim 2, wherein the predetermined indicating data has n bits provided for the respective n bits of the stored data, and a corresponding one of the n bits of the predetermined indicating data is supplied to said selecting means.

Claim 5

A semiconductor memory device as claimed in claim 3, wherein said selecting means selects said output signal from said exclusive-OR gate when said corresponding one of the n bits of the predetermined indicating data indicates a bit error.

Claim 6

A semiconductor memory device as claimed in claim 1, wherein said memory means comprises n programmable memory elements which are provided for the stored data of n bits and which store the predetermined indicating data relating to the respective n bits of the stored data.

Claim 7

A semiconductor memory device as claimed in claim 5, wherein each of the said programmable memory elements comprises a fuse ROM element.

Claim 8

A semiconductor memory device as claimed in claim 1, wherein said data area of the memory cell array is divided into n blocks and the stored data of n bits is formed by one-bit data read out from each of said n blocks.

Claim 9

A semiconductor memory device as claimed in claim 1, wherein said parity check means comprises: a parity generator which receives the stored data of n bits and generates output parity data; and an exclusive-OR gate having a first input terminal supplied with the output parity data, a second input terminal supplied with the one-bit parity code from said memory cell array, and an output terminal through which the correction data is output to said data correcting means.

Claim 10

A semiconductor memory device as claimed in claim 1, said memory means comprises: a predetermined number of programmable memory elements less than the number n for storing information relating to the predetermined indicating data; and decoder means, coupled to said programmable memory elements, for decoding said information stored in said programmable memory elements and for generating the predetermined indicating data in n bits.

Claim 11

A semiconductor memory device as claimed in claim 1, wherein the one-bit parity code stored in the parity area of said memory cell array is an even or an odd number parity bit for the stored data of n bits.

Claim 12

A semiconductor memory device, comprising: a memory cell array having a plurality of memory cells and formed by a mask ROM, said memory cell array having a data area in which a plurality of stored data of n bits is stored and a parity area in which a one-bit parity code corresponding to said plurality of stored data is stored, said data area being divided into blocks each divided into m sub-blocks; control means for supplying said memory cell array with an address including address information indicating one of said m sub-blocks and for reading out from said memory cell array the stored data and the one-bit parity code designated by the address; parity check means for determining whether the stored data read out from said memory cell array has a bit error and for generating correction data responsive thereto; memory means for storing predetermined indicating data indicative of which of the n bits in which of the m sub-blocks is defective; and data correcting means for correcting the one of the n bits of said stored data in the one of the m sub-blocks indicated by the predetermined indicating data in response to the correction data generated by said parity check means.

Claim 13

A semiconductor memory device, comprising: a memory cell array having a plurality of memory cells and formed by a mask ROM, said memory cell array having a data area in which a plurality of stored data of n bits is stored and a parity area in which a one-bit parity code corresponding to said plurality of stored data is stored, said data area being divided into blocks each divided into m sub-blocks; control means for supplying said memory cell array with an address including address information indicating one of said m sub-blocks and for reading out from said memory cell array the stored data and the one-bit parity code designated by the address; parity check means for determining whether the stored data read out from said memory cell array has a bit error and for generating correction data responsive thereto; memory means for storing predetermined indicating data indicative of which of the n bits in which of the m sub-blocks is defective; and data correcting means for correcting the one of the n bits of said stored data in the one of the m sub-blocks indicated by the predetermined indicating data in response to the correction data generated by said parity check means.

Claim 14

A semiconductor memory device as claimed in claim 11, wherein said memory means comprises: programmable memory means, provided for each of the n bits of the stored data, for storing first information indicating whether a corresponding one of the n bits of the stored data should be corrected and second information designating one of the m sub-blocks relating to a corresponding one of the blocks; address decoder means for deriving a decoded sub-block address indicating one of the m sub-blocks from the address; and logic means, coupled to said programmable memory means and said address decoder means, for deriving the predetermined indicating data indicating one of the m sub-blocks of each of the blocks relating to a bit error from the first and second information and the decoded sub-block address.

Claim 15

A semiconductor memory device as claimed in claim 12, wherein said logic means provided in said memory means comprises: decoder means for decoding the first and second information supplied from said programmable memory means and generating a decoded output; and gate means, coupled to said decoder means, for deriving the predetermined indicating data from the decoded sub-block address supplied from said address decoder means and said decoded output from said decoder means of said logic means.

Claim 16

A semiconductor memory device as claimed in claim 12, wherein said programmable memory means includes fuse ROM elements.

Claim 17

A semiconductor memory device as claimed in claim 11, wherein said data correcting means comprises a correction circuit provided for each of the n bits of the stored data, and wherein said correction circuit includes: an exclusive-OR gate having a first input terminal supplied with the correction data, a second input terminal supplied with a corresponding one of the n bits of the stored data, and an output terminal through which an output signal of said exclusive-OR gate is drawn; and selecting means for selecting one of the output signal of said exclusive-OR gate and the corresponding one of the n bits of the stored data in accordance with the predetermined indicating data from said memory means.

Claim 18

A semiconductor memory device as claimed in claim 15, wherein the predetermined indicating data has n bits provided for the respective n bits of the stored data, and a corresponding one of the n bits the predetermined indicating data is supplied to said selecting means.

Claim 19

A semiconductor memory device as claimed in claim 11, wherein said parity check means comprises: a parity generator which receives the stored data of n bits and generates output parity data; and an exclusive-OR gate having a first input terminal supplied with the output parity data, a second input terminal supplied with the one-bit parity code from said memory cell array, and an output terminal through which the correction data is output to said data correcting means.