US4615030A
Expired / Lapsed
US
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Semiconductor memory device with self correction circuit
Assignee: Oki Electric Industry Co Ltd
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Filing: 1984-04-03
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Granted: 1986-09-30
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Expires: 2004-04-03
Abstract
Abstract A semiconductor memory chip (FIG. 2) with a memory array (3) is backed-up by a self diagnosis circuit (15, 16, 17, 18, 19) so that an error of a single defective cell, or a single defective row of cells, or a single defective column of cells is automatically corrected. The backup circuit comprises a self diagnosis circuit (15) which has a one-bit memory for storing information in write phase before it is stored in a cell of the memory array (3), and comparison means for comparing the content of said one-bit memory with information immediately read out of the same cell in said write phase, a register means (16, 17) for storing the address of the memory array when said self diagnosis circuit (15) provides an error signal (P) according to the result of the comparison, and an inverter circuit (19) for inverting the output of the addressed memory cell when selected address in read phase coincides with the content of said register means (16,17). Thus, an error of a cell of the memory array is automatically corrected. Said self diagnosis circuit is mounted on the same semiconductor chip as that of a memory array itself.
Inventors
- 👤 Yutaka Kumagai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 08:57
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G06; G06F; G06F11/00; G06F11/07; G06F11/14; G11C29/88
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
335 words
A semiconductor memory device comprising: a memory array having word and bit lines arranged as a matrix and a plurality of memory cells connected between said bit and word lines; a data line; a switching circuit for selectively connecting said data line with the bit lines of the memory array; a data input circuit coupled to the data line for delivering information to the data line; and a data output circuit coupled to the data line to read out information from a selected memory cell in the memory array to an output terminal through the data line; wherein the improvement comprises; a self-diagnosis circuit coupled to the data line for storing during a writing period the information on said data line which is also stored in a selected memory cell of said memory array and for then comparing the information stored in said self-diagnosis circuit with that from said selected memory cell, said self-diagnosis circuit delivering an error signal when the two pieces of information are different from each other; a first register circuit coupled to said bit lines of said memory array for storing, in response to said error signal, an indication of the particular bit line of the memory cell which resulted in said error signal, and for subsequently delivering a first register output signal upon the reading of a memory cell on said particular bit line; a second register circuit coupled to said word lines of said memory array for storing, in response to said error signal, an indication of the particular word line of the memory cell which resulted in said error signal, and for subsequently delivering a second register output signal upon the reading of a memory cell on said particular word line; a logic circuit for producing a control signal upon receipt of both the first and second register output signals; and an output inverter circuit for inverting information fed from said data output circuit to said output terminal in response to said control signal from said logic circuit.
Claim 2
Dependent Claim
335 words
A semiconductor memory device comprising: a memory array having word and bit lines arranged as a matrix and a plurality of memory cells connected between said bit and word lines; a data line; a switching circuit for selectively connecting said data line with the bit lines of the memory array; a data input circuit coupled to the data line for delivering information to the data line; and a data output circuit coupled to the data line to read out information from a selected memory cell in the memory array to an output terminal through the data line; wherein the improvement comprises; a self-diagnosis circuit coupled to the data line for storing during a writing period the information on said data line which is also stored in a selected memory cell of said memory array and for then comparing the information stored in said self-diagnosis circuit with that from said selected memory cell, said self-diagnosis circuit delivering an error signal when the two pieces of information are different from each other; a first register circuit coupled to said bit lines of said memory array for storing, in response to said error signal, an indication of the particular bit line of the memory cell which resulted in said error signal, and for subsequently delivering a first register output signal upon the reading of a memory cell on said particular bit line; a second register circuit coupled to said word lines of said memory array for storing, in response to said error signal, an indication of the particular word line of the memory cell which resulted in said error signal, and for subsequently delivering a second register output signal upon the reading of a memory cell on said particular word line; a logic circuit for producing a control signal upon receipt of both the first and second register output signals; and an output inverter circuit for inverting information fed from said data output circuit to said output terminal in response to said control signal from said logic circuit.
Claim 3
Dependent Claim
34 words
A device according to claim 1, wherein said self-diagnosis circuit compares the information from a selected memory cell with the information stored in said self-diagnosis circuit during the latter part of a writing period.
Claim 4
Dependent Claim
15 words
A device according to claim 1, wherein said self-diagnosis circuit comprises an associative memory circuit.
Claim 5
Dependent Claim
28 words
A device according to claim 1, wherein said first register comprises a plurality of temporary memory circuits, and said second register comprises a plurality of temporary memory circuits.
Claim 6
Dependent Claim
28 words
A device according to claim 2, wherein said first register comprises a plurality of temporary memory circuits, and said second register comprises a plurality of temporary memory circuits.
Claim 7
Dependent Claim
14 words
A device according to claim 1, wherein said logic circuit comprises a NOR circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-09-29 | 1990-03-31 | 1990-09-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-09-29 | 1994-03-31 | 1994-09-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-09-29 | 1998-03-31 | 1998-09-30 | $7700.00 | Window Closed / Lapsed |