US4780875A
Expired / Lapsed
US
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Semiconductor memory with reduced size ECC circuit
Assignee: Hitachi Ltd
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Filing: 1986-08-06
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Granted: 1988-10-25
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Expires: 2006-08-06
Abstract
Abstract A semiconductor memory incorporating an ECC circuit includes a memory array, means for selecting a plurality of bits which are to be simultaneously output to the outside of the IC from a plurality of bits which are simultaneously read out from the memory array, and an error correcting circuit which constitutes the ECC circuit. The selecting means is provided in a stage previous to the error correcting circuit. In consequence, it is possible to reduce the number of bits of a signal which need to be simultaneously processed by the error correcting circuit. Accordingly, the size of the ECC circuit can be reduced.
Inventors
- 👤 Kikuo Sakai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:13
CPC Classifications
G; G11; G11C; G11C17/00; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1076
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
196 words
A semiconductor memory comprising: memory means for storing data; selecting means including means for receiving first memory data which is read out from said memory means and which is comprised of a pluarlity of sets of data each constituted by a plurality of bits, and means for selecting a predetermined bit from each of said plurality of sets of data to form second memory data comprised of a plurality of bits; and error correcting means for making error correction with respect to said second memory data, wherein said error correcting means performs said error correction on the basis of an output of a first detecting means for detecting any set of data in which an error is present among said plurality of sets of data, and on the basis of an output of second detecting means for detecting a possible error in said second memory data, wherein said first detecting means performs error detection on the basis of performing a logic operation on said first memory data and first parity bits, and said second detecting means performs error detection on the basis of performing a logic operation on said second memory data and second parity bits.
Claim 2
Dependent Claim
196 words
A semiconductor memory comprising: memory means for storing data; selecting means including means for receiving first memory data which is read out from said memory means and which is comprised of a pluarlity of sets of data each constituted by a plurality of bits, and means for selecting a predetermined bit from each of said plurality of sets of data to form second memory data comprised of a plurality of bits; and error correcting means for making error correction with respect to said second memory data, wherein said error correcting means performs said error correction on the basis of an output of a first detecting means for detecting any set of data in which an error is present among said plurality of sets of data, and on the basis of an output of second detecting means for detecting a possible error in said second memory data, wherein said first detecting means performs error detection on the basis of performing a logic operation on said first memory data and first parity bits, and said second detecting means performs error detection on the basis of performing a logic operation on said second memory data and second parity bits.
Claim 3
Dependent Claim
20 words
A semiconductor memory according to claim 1, wherein said first and second parity bits are stored in said memory means.
Claim 4
Dependent Claim
15 words
A semiconductor memory according to claim 2, wherein said memory means is a mask ROM.
Claim 5
Dependent Claim
47 words
A semiconductor memory according to claim 1, wherein each set of data is composed of four bits, the number of said plurality of sets of data being eight, the number of said first parity bits being three, and the number of said second parity bits being four.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-10-25 | 1992-04-25 | 1992-10-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-10-25 | 1996-04-25 | 1996-10-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-10-25 | 2000-04-25 | 2000-10-25 | $7700.00 | Window Closed / Lapsed |