Width-expansible memory integrity structure

Claim 2

An expansible width memory structure for concatenating a plurality of n bit data words to form a final output data word of K×n bits, said memory structure comprising: (a) a plurality of k ROM-PROM data memory chips wherein each ROM/PROM data memory chip is a duplicate-type of the other and each data memory chip stores N data words of n bits each while providing a chip output bus of n bits; (b) a single auxiliary parity ROM/PROM memory chip which is a duplicate-type of said k data memory chips, said parity memory chip storing one predetermined related parity bit for each n-bit data word in each one of said k data memory chips. (c) address bus means connected to address each one of said ROM/PROM data memory chips and said auxiliary ROM/PROM parity memory chip; (d) final output data bus means of k×n bits forming said final output data word; (e) integrity checking means for verifying the accuracy of data accessed on said final output data bus means; (f) means for selecting an operating format so as to use an odd parity or an even parity check format system, said selection means connected to said integrity checking means.

Claim 3

An expansible width memory structure for concatenating a plurality of n bit data words to form a final output data word of k× n bits, said memory structure comprising: (a) a plurality of k ROM/PROM data memory chips wherein each ROM/PROM data memory chip is a duplicate-type of the other and each data memory chip stores N data words of n bits each while providing a chip output bus of n bits; (b) a single auxiliary parity ROM/PROM memory chip which is a duplicate-type of said k data memory chips, said parity memory chip sorting one predetermined related parity bit for each n-bit data word in each one of said k data memory chips. (c) address bus means connected to address each one of said ROM/PROM data memory chips and said auxiliary ROM/PROM parity memory chip; (d) final output data bus means of k×n bits forming said final output data word; (e) integrity checking means for verifying the accuracy of data accessed on said final output data bus means, said integrity checking means including: (e1) bus means to carry accessed related parity bits from said auxiliary parity ROM/PROM memory chip to a parity check logic means; (e2) said parity check logic means for receiving accessed data words from each one of said k data memory chips via said chip output buses and including: (e2a) means for calculating the parity value of each data work accessed and comparing it with each accessed predetermined related parity bit to determine whether the parity values are inconsistent and thus indicate error; (e3) selection means to permit said parity check logic means to operate on an odd parity or an even parity format.

Claim 4

An expansible width memory structure for concatenating a plurality of n bit data words to form a final output data word of k× n bits, said memory structure comprising: (a) a plurality of k ROM/PROM data memory chips wherein each ROM/PROM data memory chip is a duplicate-type of the other and each data memory chip stores N data words of n bits each while providing a chip output bus of n bits; (b) a single auxiliary parity ROM/PROM memory chip which is a duplicate-type of said k data memory chips, said parity memory chip sorting one predetermined related parity bit for each n-bit data word in each one of said k data memory chips. (c) address bus means connected to address each one of said ROM/PROM data memory chips and said auxiliary ROM/PROM parity memory chip; (d) final output data bus means of k×n bits forming said final output data word; (e) integrity checking means for verifying the accuracy of data accessed on said final output data bus means, said integrity checking means including: (e1) bus means to carry accessed related parity bits from said auxiliary parity ROM/PROM memory chip to a parity check logic means; (e2) said parity check logic means for receiving accessed data words from each one of said k data memory chips via said chip output buses and including: (e2a) means for calculating the parity value of each data work accessed and comparing it with each accessed predetermined related parity bit to determine whether the parity values are inconsistent and thus indicate error; (e3) selection means to permit said parity check logic means to operate on an odd parity or an even parity format.