Patent US5668027A successfully refreshed from Google Patents.
US5668027A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing a MOS transistor semiconductor device
Assignee: UMC Japan Co Ltd
•
Filing: 1994-06-30
•
Granted: 1997-09-16
•
Expires: 2014-06-30
Abstract
Abstract A MOS transistor semiconductor device has a gate electrode portion with a spacer film, diffused regions diffused with dopants, and element-separating regions. After the formation of the gate on the substrate, a spacer oxide is formed adjacent to the gate. A polysilicon layer doped with the same dopants as the diffused regions is formed between the element-separating regions and the spacer film. The polysilicon layer is overlaps portions of the gate electrode and the element-separating regions that are close to the diffused regions. Thermal diffusion of the dopants from the polysilicon layer to the substrate is performed to further dope the diffused regions. After an insulation layer is formed over the polysilicon layer, connection holes are formed through the insulation layer to connect the polysilicon layer to metal interconnects. In this MOS transistor, the polysilicon layer provides holes that are larger in diameter than holes at the openings of the diffused regions that are part of the substrate surface. Therefore, the area on the silicon substrate surface occupied by diffused layers is reduced to permit semiconductor elements to be packed at a high density. The resistances of interconnects are also suppressed.
Inventors
- 👤 Masayuki Hashimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 18:51
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/601; H10P; H10P32/00; H10P32/10; H10P32/17; H10P32/171; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/63; H10D62/00; H10D62/80; H10D62/83; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10D64/259; H10D64/60; H10D64/62; H10P32/14; H10P32/1408; H10P32/1414; H10P95/00; H10P95/90
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
268 words
A method of manufacturing a MOS transistor semiconductor device having a gate electrode portion, dopant-diffused regions, and circuit element-separating regions, the gate electrode portion having a spacer-insulating film, a gate polysilicon layer and a gate cap oxide film formed on the gate polysilicon layer, said method comprising the steps of: forming the gate electrode portion of the MOS transistor semiconductor device and the circuit element-separating regions on a substrate surface of a silicon substrate, a separation region at the substrate surface separating the gate electrode portion and the circuit element-separating regions; depositing a polysilicon layer and doping the polysilicon layer with dopants onto the gate electrode portion, the separation region, and the circuit element-separating regions, the polysilicon becoming part of the dopant-diffused regions at the separation region; patterning and removing the polysilicon layer after doping the layer from portions of the gate electrode portion and the circuit element-separating regions, the polysilicon layer remaining in the dopant-diffused regions and spreading onto the gate electrode portion, onto an upper surface of the spacer-insulating film and onto a part of the gate cap oxide film and onto a part of the circuit element-separating region; depositing an insulating film on the semiconductor device; thermally treating the semiconductor device to diffuse the dopants into the substrate surface in contact with the polysilicon layer, the polysilicon layer being a diffusant source to form diffused regions at the substrate surface, the step of thermally treating planarizes the surface of the semiconductor device; removing the insulating film on a part of the polysilicon layer to form connection holes; and forming conductive interconnects in the connection holes.
Claim 2
Independent Claim
268 words
A method of manufacturing a MOS transistor semiconductor device having a gate electrode portion, dopant-diffused regions, and circuit element-separating regions, the gate electrode portion having a spacer-insulating film, a gate polysilicon layer and a gate cap oxide film formed on the gate polysilicon layer, said method comprising the steps of: forming the gate electrode portion of the MOS transistor semiconductor device and the circuit element-separating regions on a substrate surface of a silicon substrate, a separation region at the substrate surface separating the gate electrode portion and the circuit element-separating regions; depositing a polysilicon layer and doping the polysilicon layer with dopants onto the gate electrode portion, the separation region, and the circuit element-separating regions, the polysilicon becoming part of the dopant-diffused regions at the separation region; patterning and removing the polysilicon layer after doping the layer from portions of the gate electrode portion and the circuit element-separating regions, the polysilicon layer remaining in the dopant-diffused regions and spreading onto the gate electrode portion, onto an upper surface of the spacer-insulating film and onto a part of the gate cap oxide film and onto a part of the circuit element-separating region; depositing an insulating film on the semiconductor device; thermally treating the semiconductor device to diffuse the dopants into the substrate surface in contact with the polysilicon layer, the polysilicon layer being a diffusant source to form diffused regions at the substrate surface, the step of thermally treating planarizes the surface of the semiconductor device; removing the insulating film on a part of the polysilicon layer to form connection holes; and forming conductive interconnects in the connection holes.
Claim 3
Dependent Claim
47 words
The method of claim 1, wherein the step of depositing the polysilicon layer comprises the steps of: depositing an undoped layer of polysilicon on the gate electrode portion, the separation region and the circuit element-separating regions; and implanting dopants to a predetermined concentration into the polysilicon layer.
Claim 4
Dependent Claim
19 words
The method of claim 2, wherein a thickness of the polysilicon layer is between 500 Å and 3000 Å.
Claim 5
Dependent Claim
15 words
The method of claim 3, wherein the dopant used is arsenic to form NMOS transistors.
Claim 6
Dependent Claim
17 words
The method of claim 4, wherein the predetermined concentration of arsenic is 1×10 16 atoms/cm 2 .
Claim 7
Dependent Claim
15 words
The method of claim 3, wherein the dopant used is boron to form PMOS transistors.
Claim 8
Dependent Claim
17 words
The method of claim 6, wherein the predetermined concentration of boron is 5×10 15 atoms/cm 2 .
Claim 9
Dependent Claim
31 words
The method of claim 1, wherein phosphorus is implanted into the separation region to form NMOS regions, the phosphorus is implanted before forming the spacer-insulating film of the gate electrode portion.
Claim 10
Dependent Claim
19 words
The method of claim 8, wherein the phosphorus is implanted at a concentration of 1×10 13 atoms/cm 2 .
Claim 11
Dependent Claim
15 words
The method of claim 8, wherein the implantation is performed using a LDD implantation method.
Claim 12
Dependent Claim
17 words
The method of claim 1, wherein the step of depositing the insulating film uses a BPSG method.
Claim 13
Dependent Claim
11 words
The method of claim 1, wherein the conductive interconnects are aluminum.
Claim 14
Independent Claim
282 words
A method of manufacturing NMOS transistor semiconductor devices having a gate electrode portion, diffused regions, and circuit element-separating regions formed on a substrate, the method comprising the steps of: forming a gate electrode portion and circuit element-separating regions on a substrate surface of the substrate, the gate electrode portion and the element-separating portions being separated by an exposed portion of the substrate surface; forming a gate oxide cap film on the gate electrode portion; implanting a first dopant into the exposed portion of the substrate surface; forming a spacer-insulating film at an edge of the gate electrode portion and on a portion of the exposed portion of the substrate surface; depositing a polysilicon layer on the NMOS transistor; implanting a second dopant into the polysilicon layer, a diffused region being formed where the exposed portion is in contact with the polysilicon layer; removing the doped polysilicon layer from a portion of the gate electrode portion and from a portion of the circuit element-separating regions, the doped polysilicon layer remaining in the diffused region and spreading onto the gate electrode portion, onto an upper surface of the spacer-insulating film and onto a part of the gate cap oxide film and onto a part of the circuit element-separating region; depositing an insulating film on the NMOS transistor; thermally treating the NMOS transistor to planarize the insulating film and to diffuse the dopant into the substrate, the polysilicon layer being a diffusant source to form the diffused regions at the substrate surface that is contacting the polysilicon layer; forming connection holes by removing the insulating film on a part of the polysilicon layer of the diffused regions; and forming conductive interconnects in the connection holes.
Claim 15
Independent Claim
282 words
A method of manufacturing NMOS transistor semiconductor devices having a gate electrode portion, diffused regions, and circuit element-separating regions formed on a substrate, the method comprising the steps of: forming a gate electrode portion and circuit element-separating regions on a substrate surface of the substrate, the gate electrode portion and the element-separating portions being separated by an exposed portion of the substrate surface; forming a gate oxide cap film on the gate electrode portion; implanting a first dopant into the exposed portion of the substrate surface; forming a spacer-insulating film at an edge of the gate electrode portion and on a portion of the exposed portion of the substrate surface; depositing a polysilicon layer on the NMOS transistor; implanting a second dopant into the polysilicon layer, a diffused region being formed where the exposed portion is in contact with the polysilicon layer; removing the doped polysilicon layer from a portion of the gate electrode portion and from a portion of the circuit element-separating regions, the doped polysilicon layer remaining in the diffused region and spreading onto the gate electrode portion, onto an upper surface of the spacer-insulating film and onto a part of the gate cap oxide film and onto a part of the circuit element-separating region; depositing an insulating film on the NMOS transistor; thermally treating the NMOS transistor to planarize the insulating film and to diffuse the dopant into the substrate, the polysilicon layer being a diffusant source to form the diffused regions at the substrate surface that is contacting the polysilicon layer; forming connection holes by removing the insulating film on a part of the polysilicon layer of the diffused regions; and forming conductive interconnects in the connection holes.
Claim 16
Dependent Claim
11 words
The method of claim 13, wherein the first dopant is phosphorus.
Claim 17
Dependent Claim
19 words
The method of claim 14, wherein the phosphorus is implanted at a concentration of 1×10 13 atoms/cm 2 .
Claim 18
Dependent Claim
17 words
The method of claim 13, wherein the implantation of the first dopant uses an LDD implantation method.
Claim 19
Dependent Claim
11 words
The method of claim 13, wherein the second dopant is arsenic.
Claim 20
Dependent Claim
19 words
The method of claim 17, wherein the arsenic is implanted at a concentration of 1×10 16 atoms/cm 2 .
Claim 21
Dependent Claim
17 words
The method of claim 13, wherein the step of depositing the insulating film uses a BPSG method.
Claim 22
Dependent Claim
11 words
The method of claim 13, wherein the conductive interconnects are aluminum.
Claim 23
Independent Claim
269 words
A method of manufacturing PMOS transistor semiconductor devices having a gate electrode portion, diffused regions, and circuit element-separating regions formed on a substrate, the method comprising the steps of: forming a gate electrode portion and circuit element-separating regions on a substrate surface of the substrate, the gate electrode portion and the element-separating portions being separated by an exposed portion of the substrate surface; forming a gate oxide cap film on the gate electrode portion; forming a spacer-insulating film at an edge of the gate electrode portion and on a portion of the exposed portion of the substrate surface; depositing a polysilicon layer on the PMOS transistor; implanting a dopant into the polysilicon layer, a diffused region being formed where the exposed portion is in contact with the polysilicon layer; removing the doped polysilicon layer from a portion of the gate electrode portion and from a portion of the circuit element-separating regions, the doped polysilicon layer remaining in the diffused region and spreading onto the gate electrode portion, onto an upper surface of the spacer-insulating film and onto a part of the gate cap oxide film and onto a part of the circuit element-separating region; depositing an insulating film on the PMOS transistor; thermally treating the PMOS transistor to planarize the insulating film and to diffuse the dopant into the substrate, the polysilicon layer being a diffusant source to form the diffused regions at the substrate surface that is contacting the polysilicon layer; forming connection holes by removing the insulating film on a part of the polysilicon layer of the diffused regions; and forming conductive interconnects in the connection holes.
Claim 24
Independent Claim
269 words
A method of manufacturing PMOS transistor semiconductor devices having a gate electrode portion, diffused regions, and circuit element-separating regions formed on a substrate, the method comprising the steps of: forming a gate electrode portion and circuit element-separating regions on a substrate surface of the substrate, the gate electrode portion and the element-separating portions being separated by an exposed portion of the substrate surface; forming a gate oxide cap film on the gate electrode portion; forming a spacer-insulating film at an edge of the gate electrode portion and on a portion of the exposed portion of the substrate surface; depositing a polysilicon layer on the PMOS transistor; implanting a dopant into the polysilicon layer, a diffused region being formed where the exposed portion is in contact with the polysilicon layer; removing the doped polysilicon layer from a portion of the gate electrode portion and from a portion of the circuit element-separating regions, the doped polysilicon layer remaining in the diffused region and spreading onto the gate electrode portion, onto an upper surface of the spacer-insulating film and onto a part of the gate cap oxide film and onto a part of the circuit element-separating region; depositing an insulating film on the PMOS transistor; thermally treating the PMOS transistor to planarize the insulating film and to diffuse the dopant into the substrate, the polysilicon layer being a diffusant source to form the diffused regions at the substrate surface that is contacting the polysilicon layer; forming connection holes by removing the insulating film on a part of the polysilicon layer of the diffused regions; and forming conductive interconnects in the connection holes.
Claim 25
Dependent Claim
10 words
The method of claim 21, wherein the dopant is boron.
Claim 26
Dependent Claim
16 words
The method of claim 22, wherein the concentration of boron is 5×10 15 atoms/cm 2 .
Claim 27
Dependent Claim
17 words
The method of claim 21, wherein the step of depositing the insulating film uses a BPSG method.
Claim 28
Dependent Claim
11 words
The method of claim 21, wherein the conductive interconnects are aluminum.
References Cited (Backward Citations)
US4041518A
Cited
JPS53121580A
Cited
US4353085A
Cited
JPS5789253A
Cited
JPS57196573A
Cited
JPS5886771A
Cited
JPS5947768A
Cited
US4822754A
Cited
JPS6012772A
Cited
US4735916A
Cited
US4826782A
Cited
US4931845A
Cited
US5113234A
Cited
JPH022136A
Cited
US5079180A
Cited
US5314832A
Cited
US5547885A
Cited
US5168072A
Cited
US5395787A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-15 | 2001-03-17 | 2001-09-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-15 | 2005-03-17 | 2005-09-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-15 | 2009-03-17 | 2009-09-16 | $7700.00 | Window Closed / Lapsed |