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US5668025A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of making a FET with dielectrically isolated sources and drains

Assignee: STMicroelectronics lnc USA
•
Filing: 1995-02-28
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Granted: 1997-09-16
•
Expires: 2015-02-28
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Abstract

Abstract The present application provides a CMOS device and process in which the source/drain regions are polysilicon, and are dielectrically isolated from the well regions. This structure can be obtained, for example, by depositing the first layer of polysilicon under very high temperature conditions (essentially the same as those normally used for epitaxial deposition), so that the first polysilicon layer is formed epitaxially (as monocrystalline silicon) over exposed regions, and as polycrystalline material over oxide. An oxide is grown on the surface of the deposited layer, and a second polysilicon layer is then deposited, under normal conditions, to form the gate layer. After the second polysilicon layer has been patterned, source/drain implants are then made into the first (intrinsic) polysilicon layer to form source/drain implants. Thus, the first polysilicon layer will contain both N+ and P+ regions, and if desired, may also include intrinsic regions.

Inventors

  • 👤 Richard A. Blanchard

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 18:22
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/027; H10D30/0278; H10D30/031; H10D30/0321; H10D30/0323; H10D30/60; H10D30/67; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6744; H10D30/6758; H10D62/00; H10D62/10; H10D62/113; H10D62/115; H10D62/116; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D62/292; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0167; H10D84/017; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/854; H10D86/00; H10D86/01

Claims Analysis

Total Claims: 35
Claim 1
Independent Claim 228 words
A method for fabricating integrated circuit devices, comprising the steps of: (a.) providing a substrate which includes at least one monolithic body of semiconductor material; (b.) covering part of the surface of said monolithic body with a patterned dielectric layer, said patterned dielectric layer leaving said monolithic body exposed in transistor channel locations; (c.) forming additional semiconductor material, as monocrystalline semiconductor material on said monolithic body in said transistor channel locations, and as polycrystalline semiconductor material elsewhere; said additional semiconductor material being formed to a thickness which is greater than the thickness of said patterned dielectric layer; (d.) patterning said additional semiconductor material to form a patterned thin film layer, and forming a gate dielectric on said additional semiconductor material; (e.) forming an additional patterned conductive thin film layer on said gate dielectric; and (f.) implanting dopants of a desired conductivity type into said additional semiconductor material where exposed by said additional patterned conductive thin film layer; said steps (e.) and (f.) forming a completed transistor wherein a monocrystalline portion of said additional semiconductor material beneath said additional patterned conductive thin film layer forms a transistor channel region, said additional patterned conductive thin film layer provides an insulated gate which is coupled to said transistor channel region, and said implanting step (f.) forms source and drain regions which lie entirely within polycrystalline portions of said additional semiconductor material.
Claim 2
Independent Claim 228 words
A method for fabricating integrated circuit devices, comprising the steps of: (a.) providing a substrate which includes at least one monolithic body of semiconductor material; (b.) covering part of the surface of said monolithic body with a patterned dielectric layer, said patterned dielectric layer leaving said monolithic body exposed in transistor channel locations; (c.) forming additional semiconductor material, as monocrystalline semiconductor material on said monolithic body in said transistor channel locations, and as polycrystalline semiconductor material elsewhere; said additional semiconductor material being formed to a thickness which is greater than the thickness of said patterned dielectric layer; (d.) patterning said additional semiconductor material to form a patterned thin film layer, and forming a gate dielectric on said additional semiconductor material; (e.) forming an additional patterned conductive thin film layer on said gate dielectric; and (f.) implanting dopants of a desired conductivity type into said additional semiconductor material where exposed by said additional patterned conductive thin film layer; said steps (e.) and (f.) forming a completed transistor wherein a monocrystalline portion of said additional semiconductor material beneath said additional patterned conductive thin film layer forms a transistor channel region, said additional patterned conductive thin film layer provides an insulated gate which is coupled to said transistor channel region, and said implanting step (f.) forms source and drain regions which lie entirely within polycrystalline portions of said additional semiconductor material.
Claim 3
Dependent Claim 11 words
The method of claim 1, wherein said semiconductor material is silicon.
Claim 4
Dependent Claim 19 words
The method of claim 1, wherein said patterned dielectric layer and said gate dielectric both consist of silicon dioxide.
Claim 5
Dependent Claim 29 words
The method of claim 1, further comprising the additional step of forming a sidewall spacer on said additional patterned conductive thin film layer prior to said implanting step (f.).
Claim 6
Dependent Claim 22 words
The method of claim 1, further comprising the additional step of doping said additional semiconductor material prior to said forming step (e.).
Claim 7
Dependent Claim 31 words
The method of claim 1, further comprising the additional step of forming at least one first-conductivity-type surface region and at least one second-conductivity-type surface region prior to said covering step (b.).
Claim 8
Dependent Claim 36 words
The method of claim 1, further comprising the additional step of forming a patterned thick field dielectric region, which is more than twice as thick as said patterned dielectric layer, prior to said covering step (b.).
Claim 9
Dependent Claim 17 words
The method of claim 1, wherein said additional patterned conductive thin film layer comprises polycrystalline semiconductor material.
Claim 10
Dependent Claim 22 words
The method of claim 1, wherein said completed transistor is asymmetrical, and wherein said source and drain regions have different diffusion profiles.
Claim 11
Dependent Claim 16 words
The method of claim 1, wherein said patterned dielectric layer is not self-aligned to said gate.
Claim 12
Dependent Claim 24 words
The method of claim 1, wherein part of said polycrystalline semiconductor material is left undoped to provide intrinsic material having a high sheet resistance.
Claim 13
Independent Claim 225 words
A method for fabricating integrated circuit devices, comprising the steps of: (a.) providing a substrate which includes at least one monolithic body of semiconductor material; (b.) covering part of the surface of said monolithic body with a patterned dielectric layer, said patterned dielectric layer leaving said monolithic body exposed in transistor channel locations; (c.) depositing additional semiconductor material overall, as epitaxially matched monocrystalline semiconductor material on said monolithic body in said transistor channel locations, and as polycrystalline semiconductor material elsewhere; said additional semiconductor material being formed to a thickness which is greater than the thickness of said patterned dielectric layer; (d.) patterning said additional semiconductor material to form a patterned thin film layer, and forming a gate dielectric on said additional semiconductor material; (e.) forming an additional patterned conductive thin film layer, comprising polycrystalline semiconductor material, on said gate dielectric; and (f.) implanting dopants of a desired conductivity type into said additional semiconductor material where exposed by said additional patterned conductive thin film layer; said steps (e.) and (f.) forming a complete transistor wherein a monocrystalline portion of said additional semiconductor material beneath said additional patterned conductive thin film layer forms a transistor channel region, and said implanting step (f.) forms source and drain regions which lie entirely within polycrystalline portions of said additional semiconductor material and which lie entirely over said patterned dielectric layer.
Claim 14
Independent Claim 225 words
A method for fabricating integrated circuit devices, comprising the steps of: (a.) providing a substrate which includes at least one monolithic body of semiconductor material; (b.) covering part of the surface of said monolithic body with a patterned dielectric layer, said patterned dielectric layer leaving said monolithic body exposed in transistor channel locations; (c.) depositing additional semiconductor material overall, as epitaxially matched monocrystalline semiconductor material on said monolithic body in said transistor channel locations, and as polycrystalline semiconductor material elsewhere; said additional semiconductor material being formed to a thickness which is greater than the thickness of said patterned dielectric layer; (d.) patterning said additional semiconductor material to form a patterned thin film layer, and forming a gate dielectric on said additional semiconductor material; (e.) forming an additional patterned conductive thin film layer, comprising polycrystalline semiconductor material, on said gate dielectric; and (f.) implanting dopants of a desired conductivity type into said additional semiconductor material where exposed by said additional patterned conductive thin film layer; said steps (e.) and (f.) forming a complete transistor wherein a monocrystalline portion of said additional semiconductor material beneath said additional patterned conductive thin film layer forms a transistor channel region, and said implanting step (f.) forms source and drain regions which lie entirely within polycrystalline portions of said additional semiconductor material and which lie entirely over said patterned dielectric layer.
Claim 15
Dependent Claim 11 words
The method of claim 12, wherein said semiconductor material is silicon.
Claim 16
Dependent Claim 19 words
The method of claim 12, wherein said patterned dielectric layer and said gate dielectric both consist of silicon dioxide.
Claim 17
Dependent Claim 29 words
The method of claim 12, further comprising the additional step of forming a sidewall spacer on said additional patterned conductive thin film layer prior to said implanting step (f.).
Claim 18
Dependent Claim 22 words
The method of claim 12, further comprising the additional step of doping said additional semiconductor material prior to said forming step (e.).
Claim 19
Dependent Claim 31 words
The method of claim 12, further comprising the additional step of forming at least one first-conductivity-type surface region and at least one second-conductivity-type surface region prior to said covering step (b.).
Claim 20
Dependent Claim 36 words
The method of claim 12, further comprising the additional step of forming a patterned thick field dielectric region, which is more than twice as thick as said patterned dielectric layer, prior to said covering step (b.).
Claim 21
Dependent Claim 17 words
The method of claim 12, wherein said additional patterned conductive thin film layer comprises polycrystalline semiconductor material.
Claim 22
Dependent Claim 22 words
The method of claim 12, wherein said completed transistor is asymmetrical, and wherein said source and drain regions have different diffusion profiles.
Claim 23
Dependent Claim 16 words
The method of claim 12, wherein said patterned dielectric layer is not self-aligned to said gate.
Claim 24
Dependent Claim 24 words
The method of claim 12, wherein part of said polycrystalline semiconductor material is left undoped to provide intrinsic material having a high sheet resistance.
Claim 25
Independent Claim 277 words
A method for fabricating CMOS integrated circuit devices, comprising the steps of: (a.) providing a substrate which includes at least one monolithic body of semiconductor material, having at least one first-conductivity-type surface region and at least one second-conductivity-type surface region; (b.) covering part of the surface of said monolithic body with a patterned dielectric layer, said patterned dielectric layer leaving said monolithic body exposed in transistor channel locations; (c.) forming additional semiconductor material, as monocrystalline semiconductor material on said monolithic body in said transistor channel locations, and as polycrystalline semiconductor material elsewhere; said additional semiconductor material being formed to a thickness which is greater than the thickness of said patterned dielectric layer; (d.) patterning said additional semiconductor material to form a patterned thin film layer, and forming a gate dielectric on said additional semiconductor material; (e.) forming an additional patterned conductive thin film layer on said gate dielectric; and (f.) implanting dopants of said first conductivity type over locations of said second-conductivity-type regions of said monolithic body, and implanting dopants of said second conductivity type over locations of said first-conductivity-type regions of said monolithic body, to dope said additional semiconductor material where exposed by said additional patterned conductive thin film layer; said steps (e.) and (f.) forming a completed transistor wherein a monocrystalline portion of said additional semiconductor material beneath said additional patterned conductive thin film layer forms a transistor channel region, said additional patterned conductive thin film layer provides an insulated gate which is coupled to said transistor channel region, and said implanting step (f.) forms source and drain regions which lie entirely within polycrystalline portions of said additional semiconductor material over said patterned dielectric layer.
Claim 26
Independent Claim 277 words
A method for fabricating CMOS integrated circuit devices, comprising the steps of: (a.) providing a substrate which includes at least one monolithic body of semiconductor material, having at least one first-conductivity-type surface region and at least one second-conductivity-type surface region; (b.) covering part of the surface of said monolithic body with a patterned dielectric layer, said patterned dielectric layer leaving said monolithic body exposed in transistor channel locations; (c.) forming additional semiconductor material, as monocrystalline semiconductor material on said monolithic body in said transistor channel locations, and as polycrystalline semiconductor material elsewhere; said additional semiconductor material being formed to a thickness which is greater than the thickness of said patterned dielectric layer; (d.) patterning said additional semiconductor material to form a patterned thin film layer, and forming a gate dielectric on said additional semiconductor material; (e.) forming an additional patterned conductive thin film layer on said gate dielectric; and (f.) implanting dopants of said first conductivity type over locations of said second-conductivity-type regions of said monolithic body, and implanting dopants of said second conductivity type over locations of said first-conductivity-type regions of said monolithic body, to dope said additional semiconductor material where exposed by said additional patterned conductive thin film layer; said steps (e.) and (f.) forming a completed transistor wherein a monocrystalline portion of said additional semiconductor material beneath said additional patterned conductive thin film layer forms a transistor channel region, said additional patterned conductive thin film layer provides an insulated gate which is coupled to said transistor channel region, and said implanting step (f.) forms source and drain regions which lie entirely within polycrystalline portions of said additional semiconductor material over said patterned dielectric layer.
Claim 27
Dependent Claim 11 words
The method of claim 23, wherein said semiconductor material is silicon.
Claim 28
Dependent Claim 19 words
The method of claim 23, wherein said patterned dielectric layer and said gate dielectric both consist of silicon dioxide.
Claim 29
Dependent Claim 29 words
The method of claim 23, further comprising the additional step of forming a sidewall spacer on said additional patterned conductive thin film layer prior to said implanting step (f.).
Claim 30
Dependent Claim 22 words
The method of claim 23, further comprising the additional step of doping said additional semiconductor material prior to said forming step (e.).
Claim 31
Dependent Claim 31 words
The method of claim 23, further comprising the additional step of forming at least one first-conductivity-type surface region and at least one second-conductivity-type surface region prior to said covering step (b.).
Claim 32
Dependent Claim 36 words
The method of claim 23, further comprising the additional step of forming a patterned thick field dielectric region, which is more than twice as thick as said patterned dielectric layer, prior to said covering step (b.).
Claim 33
Dependent Claim 22 words
The method of claim 23, wherein said completed transistor is asymmetrical, and wherein said source and drain regions have different diffusion profiles.
Claim 34
Dependent Claim 16 words
The method of claim 23, wherein said patterned dielectric layer is not self-aligned to said gate.
Claim 35
Dependent Claim 24 words
The method of claim 23, wherein part of said polycrystalline semiconductor material is left undoped to provide intrinsic material having a high sheet resistance.

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2000-09-15 2001-03-17 2001-09-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2004-09-15 2005-03-17 2005-09-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2008-09-15 2009-03-17 2009-09-16 $7700.00 Window Closed / Lapsed

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