Patent US5158062A successfully refreshed from Google Patents.
Patent US5664165A successfully refreshed from Google Patents.
US5664165A
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Generation of a synthetic clock signal in synchronism with a high frequency clock signal and corresponding to a low frequency clock signal
Assignee: International Business Machines Corp
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Filing: 1995-04-19
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Granted: 1997-09-02
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Expires: 2015-04-19
Abstract
Abstract A system and method for generating a synthetic clock signal in synchronism with both a high frequency clock signal and low frequency clock signal, where the rising and falling edges of the low frequency clock signal are subject to material skew. The frequency ratio between the high and low frequency clock signals is derived by sampling the low frequency clock signal at the frequency of the high frequency cloak signal. The synthesized low frequency clock signal is generated directly from the high frequency clock signal using the determined relative frequency ratio. The synthetic clock signal is also in synchronism with the low frequency clock signal. Since the synthetic clock signal is derived directly from the high frequency clock signal, it is not subject to the skew problems of the low frequency clock signal.
Inventors
- 👤 Sean Eugene Curry
- 👤 Barry Joe Wolford
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 11:03
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/12; H; H04; H04L; H04L7/00; H04L7/0054
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
99 words
In a data processing system having multiple clock signals, where first and second clock signals may differ in frequency, apparatus for generating a synthetic clock signal, comprising: means for determining a relative frequency between the second clock signal and the first clocking signal using the first clock signal; means for selecting a frequency ratio for the synthetic clock signal based upon the relative frequency determined; and means for generating the synthetic clock signal, at the frequency of the second clock signal and in synchronism with the first clock signal, by relating the frequency ratio to the first clock signal.
Claim 2
Dependent Claim
99 words
In a data processing system having multiple clock signals, where first and second clock signals may differ in frequency, apparatus for generating a synthetic clock signal, comprising: means for determining a relative frequency between the second clock signal and the first clocking signal using the first clock signal; means for selecting a frequency ratio for the synthetic clock signal based upon the relative frequency determined; and means for generating the synthetic clock signal, at the frequency of the second clock signal and in synchronism with the first clock signal, by relating the frequency ratio to the first clock signal.
Claim 3
Dependent Claim
23 words
The apparatus recited in claim 1, wherein the synthetic clock signal from the means for generating is fixed after initialization of the system.
Claim 4
Dependent Claim
24 words
The apparatus recited in claim 2, wherein the means for determining samples the second clock signal at the frequency of the first clock signal.
Claim 5
Dependent Claim
30 words
The apparatus recited in claim 3, wherein the sampling is accomplished in synchronism with the first clock signal as applied to a phase shifted version of the second clock signal.
Claim 6
Dependent Claim
19 words
The apparatus recited in claim 4, wherein the means for selecting decodes a binary pattern derived by the sampling.
Claim 7
Dependent Claim
51 words
The apparatus recited in claim 5, wherein the apparatus is internal to an integrated circuit chip, the clock signals originate external to the integrated circuit chip, and the edges of the second clock signal conform to a specification permitting material skew in relation to the edges of the first clock signal.
Claim 8
Dependent Claim
97 words
In a data processing system having multiple clock signals, wherein first and second clock signals may differ in frequency, a method for generating a synthetic clock signal, comprising the steps of: determining a relative frequency between the second clock signal and the first clock signal using the first clock signal; selecting a frequency ratio for the synthetic clock signal based upon the relative frequency determined; and generating the synthetic clock signal, at the frequency of the second clock signal and in synchronism with the first clock signal, by relating the frequency ratio to the first clock signal.
Claim 9
Dependent Claim
97 words
In a data processing system having multiple clock signals, wherein first and second clock signals may differ in frequency, a method for generating a synthetic clock signal, comprising the steps of: determining a relative frequency between the second clock signal and the first clock signal using the first clock signal; selecting a frequency ratio for the synthetic clock signal based upon the relative frequency determined; and generating the synthetic clock signal, at the frequency of the second clock signal and in synchronism with the first clock signal, by relating the frequency ratio to the first clock signal.
Claim 10
Dependent Claim
19 words
The method recited in claim 7, wherein the generated synthetic clock signal is fixed after initialization of the system.
Claim 11
Dependent Claim
24 words
The method recited in claim 8, wherein the step of determining samples the second clock signal at the frequency at the first clock signal.
Claim 12
Dependent Claim
30 words
The method recited in claim 9, wherein the sampling is accomplished in synchronism with the first clock signal as applied to a phase shifted version of the second clock signal.
Claim 13
Dependent Claim
19 words
The method recited in claim 10, wherein the step of selecting decodes a binary pattern derived by the sampling.
Claim 14
Dependent Claim
52 words
The method recited in claim 11, wherein the method is performed internal to and integrated circuit chip, the clock signals originate external to the integrated circuit chip, and the edges of the second clock signal conform to a specification permitting material skew in relation to the edges of the first clock signal.
Claim 15
Dependent Claim
100 words
In a data processing system having a high frequency processor clock signal and a low frequency input/output (I/O) clock signal, a circuit for generating a synthetic I/O clock signal, comprising: means for sampling the I/O clock signal in synchronism with the processor clock signal; means for selecting a frequency ratio for the synthetic I/O clock signal based upon a decode of the sampled I/O clock signal; and means for generating the synthetic I/O clock signal at the frequency of the I/O signal and in synchronism with the processor clock signal, by relating the frequency ratio to the processor clock signal.
Claim 16
Dependent Claim
100 words
In a data processing system having a high frequency processor clock signal and a low frequency input/output (I/O) clock signal, a circuit for generating a synthetic I/O clock signal, comprising: means for sampling the I/O clock signal in synchronism with the processor clock signal; means for selecting a frequency ratio for the synthetic I/O clock signal based upon a decode of the sampled I/O clock signal; and means for generating the synthetic I/O clock signal at the frequency of the I/O signal and in synchronism with the processor clock signal, by relating the frequency ratio to the processor clock signal.
Claim 17
Dependent Claim
24 words
The circuit recited in claim 13, wherein the synthetic I/O clock signal from the means for generating is fixed after initialization of the system.
Claim 18
Dependent Claim
21 words
The circuit recited in claim 14, wherein the means for sampling samples a phase shifted version of the I/O clock signal.
Claim 19
Dependent Claim
51 words
The circuit recited in claim 15, wherein the circuit is integral to an integrated circuit chip, the clock signals originate external to the integrated circuit chip, and the edges of the I/O clock signal conform to a specification permitting material skew in relation to the edges of the processor clock signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-01 | 2001-03-03 | 2001-09-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-01 | 2005-03-03 | 2005-09-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-01 | 2009-03-03 | 2009-09-02 | $7700.00 | Window Closed / Lapsed |