Latent defect handling in EEPROM devices

Claim 2

In an integrated circuit memory device having an array of addressable semiconductor electrically erasable and programmable (EEPROM) memory cells, the memory cell being of the type including a substrate, a source, a drain, and a control gate electrode receptive to specific voltage conditions for memory operations such as reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, said array of memory cells being organized in a two-dimensional array addressable by access lines, wherein a word line there among is connected to the control gates of each row of memory cells, and a pair of bit lines there among are respectively connected to the sources and the drains of each column of memory cells, such that the two-dimensional array is addressable by rows and columns of access lines during memory operations by specific voltage conditions thereon, said integrated circuit memory device further comprising: word line current detector means for measuring leakage current in a word line connectable thereto; and means for connecting said detector means to a word line under test to measure the leakage current therein, whereby a defective word line is identifiable by said leakage current exceeding a predetermined level.

Claim 3

An integrated circuit memory device as in claim 1, wherein the memory cell being of the type including an erase electrode, and said access lines include erase lines, wherein an erase line is connected to the erase electrodes of each sector of cells consisting of one or more rows of memory cells, said integrated circuit memory device further comprising: erase line detector means for measuring leakage current in an erase line connectable thereto; and means for connecting said detector means to an erase line under test to measure the leakage current therein, whereby a defective erase line is identifiable by said leakage current exceeding a predetermined level.

Claim 4

In an integrated circuit memory device having an array of addressable semiconductor electrically erasable and programmable (EEPROM) memory cells, the memory cell being of the type including a substrate, a source, a drain, and a control gate electrode receptive to specific voltage conditions for memory operations such as reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, said array of memory cells being organized in a two-dimensional array addressable by access lines, wherein one type of access line being word lines connected to the control gates of each row of memory cells, and another type of access line being bit lines connected to the sources or drains of each column of memory cells, such that the two-dimensional array is addressable by rows and columns of access lines during memory operations by specific voltage conditions thereon, a method for detecting word line defects in the EEPROM memory array comprising the steps of: establishing a predetermined potential difference for a word line under test relative to the substrate and a set of access lines that are capable of being shorted to said word line under test; detecting a short circuit condition at said word line under test when a leakage current measured therein exceeded a predetermined level; and repeating the steps of establishing a predetermined potential difference and detecting a short circuit condition for every word line to be tested in the EEPROM memory array.

Claim 5

In an integrated circuit memory device having an array of addressable semiconductor electrically erasable and programmable (EEPROM) memory cells, the memory cell being of the type including a substrate, a source, a drain, and a control gate electrode receptive to specific voltage conditions for memory operations such as reading, programming and erasing of data in the cell, and having a floating gate capable of retaining a specific charge level corresponding to a specific memory state of the cell, said array of memory cells being organized in a two-dimensional array addressable by access lines, wherein one type of access line being word lines connected to the control gates of each row of memory cells, and another type of access line being bit lines connected to the sources or drains of each column of memory cells, such that the two-dimensional array is addressable by rows and columns of access lines during memory operations by specific voltage conditions thereon, a method for detecting word line defects in the EEPROM memory array comprising the steps of: establishing a predetermined potential difference for a word line under test relative to the substrate and a set of access lines that are capable of being shorted to said word line under test; detecting a short circuit condition at said word line under test when a leakage current measured therein exceeded a predetermined level; and repeating the steps of establishing a predetermined potential difference and detecting a short circuit condition for every word line to be tested in the EEPROM memory array.

Claim 6

A method for detecting word line defects in an EEPROM memory array as in claim 3, wherein the method is applied to a set of word lines under test simultaneously.

Claim 7

A method for detecting defects among a set of word lines in an EEPROM memory array as in claim 4, wherein said set of word lines includes all the word lines in the EEPROM memory array.

Claim 8

A method for detecting word line defects in an EEPROM memory array as in claim 1, wherein said method is implemented during use of the EEPROM memory array at preselected times.

Claim 9

A method for detecting word line defects in an EEPROM memory array as in claim 6, wherein the method is applied to a set of word lines under test simultaneously.

Claim 10

A method for detecting defects among a set of word lines in an EEPROM memory array as in claim 7, wherein said set of word lines consists of all the word lines in the EEPROM memory array.

Claim 11

A method for detecting word line defects in the EEPROM memory array as in claim 3, wherein: the memory cell is of the type including an erase electrode; the memory array is organized into sectors of cells consisting of one or more rows of cells that are erasable together; and the access lines include erase lines connected to the erase electrodes of each sector of cells.

Claim 12

A method for detecting word line defects in the EEPROM memory array as in claim 9, wherein the step of raising the word line under test to a predetermined potential includes grounding a set of access lines that are capable of being shorted to said word line under test, so as to determine if the word line under test is shorted to the substrate or any one of said set of access lines.

Claim 13

A method for detecting word line defects in the EEPROM memory array as in claim 9, wherein the step of raising the word line under test to a predetermined potential includes, among said set of access lines, grounding the word lines therein while floating the erase lines and bit lines therein, so as to determine if the word line under test is shorted to the substrate or any one of the word lines therein.

Claim 14

A method for detecting word line defects in the EEPROM memory array as in claim 9, wherein the step of raising the word line under test to a predetermined potential includes, among said set of access lines, grounding the bit lines therein while floating the word lines and erase lines therein, so as to determine if the word line under test is shorted to the substrate or any one of the bit lines therein.

Claim 15

A method for detecting word line defects in the EEPROM memory array as in claim 9, wherein the step of raising the word line under test to a predetermined potential includes, among said set of access lines, grounding the erase lines therein while floating the word lines and bit lines therein, so as to determine if the word line under test is shorted to the substrate or any one of the erase lines therein.

Claim 16

A method for detecting word line defects in an EEPROM memory array as in claim 9, further including a sequence of tests such that in each test the step of raising the word line under test to a predetermined potential includes, among said set of access lines, a different combination of grounding or floating of each type of lines such as word lines or bit lines therein, so as to identify what type of line the word line under test is shorted to.

Claim 17

A method for detecting word line defects in an EEPROM memory array as in claim 3, further including a sequence of tests such that in each test the step of raising the word line under test to a predetermined potential includes, among said set of access lines, a different combination of grounding or floating of each type of lines such as word lines or bit lines therein, so as to identify what type of line the word line under test is shorted to.