Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
108 words
In a semiconductor memory device comprising a plurality of word lines which are arranged in parallel, and word line drive means for respectively driving said word lines, said semiconductor memory device further comprises word line test means for receiving a test signal, and for producing an output signal, the level of said output signal being high when said test signal is active and low when said test signal is not active, preselected ones of said word line drive means being coupled to an output of said test means, and, when the associated word lines are not to be driven, applying said output signal to said associated word lines.
Claim 2
Dependent Claim
22 words
A semiconductor memory device according to claim 1, wherein said preselected word line drive means are ones connected to odd-numbered word lines.
Claim 3
Dependent Claim
22 words
A semiconductor memory device according to claim 1, wherein said preselected word line drive means are ones connected to even-numbered word lines.
Claim 4
Dependent Claim
76 words
In a semiconductor memory device comprising a plurality of bit lines which are arranged in parallel, said semiconductor memory device further comprises bit line test means for receiving a test signal, and for, when said test signal is active, applying a first output signal to odd-numbered ones of said bit lines and a second output signal to even-numbered ones of said bit lines, said first and second output signals being different in level from each other.
Claim 5
Dependent Claim
34 words
A semiconductor memory device according to claim 4, wherein said bit line test means comprises switch means for, when said test signal is active, connecting said bit line test means to said bit lines.
Claim 6
Dependent Claim
173 words
In a semiconductor memory device comprising a plurality of word lines which are arranged in parallel, a plurality of bit lines which are arranged in parallel, and word line drive means for respectively driving said word lines, said semiconductor memory device further comprises: word line test means for receiving a test signal, and for producing an output signal, the level of said output signal being high when said test signal is active and low when said test signal is not active; and bit line test means for receiving a test signal, and for, when said test signal is active, applying a first output signal to odd-numbered ones of said bit lines and a second output signal to even-numbered ones of said bit lines, said first and second output signals being different in level from each other, preselected ones of said word line drive means being coupled to an output of said test means, and, when the associated word lines are not to be driven, applying said output signal to said associated word lines.
Claim 7
Dependent Claim
22 words
A semiconductor memory device according to claim 6, wherein said preselected word line drive means are ones connected to odd-numbered word lines.
Claim 8
Dependent Claim
22 words
A semiconductor memory device according to claim 6, wherein said preselected word line drive means are ones connected to even-numbered word lines.
Claim 9
Dependent Claim
34 words
A semiconductor memory device according to claim 6, wherein said bit line test means comprises switch means for, when said test signal is active, connecting said bit line test means to said bit lines.
Claim 10
Dependent Claim
133 words
A semiconductor memory device comprising a matrix array of memory cells, a set of parallel drive lines, connected to respective rows or columns of cells of said array, a corresponding set of line drive circuits for driving respective said drive lines, and line test means adapted to test for short circuits between said drive lines, said line test means being operable in a line test operation to apply a line test signal via an output line thereof to preselected ones of said line drive circuits, each of said preselected line drive circuits being adapted to apply said line test signal to the associated drive line if that line is not being driven, means being provided for measuring a current flowing in said output line during said test operation due to such short circuits.
Claim 11
Dependent Claim
78 words
Apparatus for testing a semiconductor memory device having a plurality of parallel drive lines for short circuit between different said lines, said apparatus being operable in a test operation to apply via a supply line a test voltage to a first group of alternate said drive lines, and means for measuring a current flowing in said supply line due to short circuits between said first group of alternate drive lines and a second group of alternate drive lines.