Patent US5657537A successfully refreshed from Google Patents.
US5657537A
Expired / Lapsed
US
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Method for fabricating a stack of two dimensional circuit modules
Assignee: General Electric Co
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Filing: 1995-05-30
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Granted: 1997-08-19
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Expires: 2015-05-30
Abstract
Abstract A method for fabricating a stack of circuit modules includes providing a plurality of substrates having module interconnection layers. Each of the substrates has a circuit chip with chip pads positioned therein and an electrically conductive feed-through line extending from a first surface of the substrate to a second surface of the substrate with the first surface being perpendicular to the second surface. Each of the module interconnection layers is situated over a respective first surface of each of the substrates and includes a module dielectric layer having module vias therein and a module pattern of electrical conductors extending through the module vias to couple the selected chip pads to the feed-through line. The plurality of substrates are stacked. A side interconnection layer is applied over a side surface including the second surfaces of the substrates. The side interconnection layer includes a side dielectric layer having side vias therein aligned with predetermined ones of the feed-through lines and a side pattern of electrical conductors extending through the side vias.
Inventors
- 👤 Richard Joseph Saia
- 👤 Bernard Gorowitz
- 👤 Kevin Matthew Durocher
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 20:32
CPC Classifications
H; H10; H10W; H10W90/00; H05; H05K; H05K1/00; H05K1/02; H05K1/14; H05K1/144; H05K3/00; H05K3/40; H05K3/403; H10W70/00; H10W70/099; H10W70/60; H10W70/611; H10W70/614; H05K1/03; H05K1/0306; H05K2201/00; H05K2201/09; H05K2201/09209; H05K2201/095; H05K2201/09581; H05K3/46; H05K3/4611; H05K3/4626; H05K3/4629; H05K3/4685; H10W72/00; H10W72/071; H10W72/073; H10W72/07331; H10W72/30; H10W72/351; H10W72/353; H10W72/354; H10W72/834; H10W90/701; H10W90/721; H10W90/722; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49126
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
175 words
A method for fabricating a stack of two dimensional circuit modules, the method comprising the steps of: providing a plurality of substrates having module interconnection layers, each of the substrates having a circuit chip with chip pads positioned therein and an electrically conductive feed-through line extending therethrough from a first surface of the substrate to a second surface of the substrate, the first surface being perpendicular to the second surface, each of the module interconnection layers being situated over a respective first surface of each of the substrates and comprising a module dielectric layer having module vias therein and a module pattern of electrical conductors extending through the module vias to couple the selected chip pads to the feed-through line; stacking the plurality of substrates; and applying a side interconnection layer over a side surface including the second surfaces of the substrates, the side interconnection layer comprising a side dielectric layer having side vias therein aligned with predetermined ones of the feed-through lines and a side pattern of electrical conductors extending through the side vias.
Claim 2
Independent Claim
175 words
A method for fabricating a stack of two dimensional circuit modules, the method comprising the steps of: providing a plurality of substrates having module interconnection layers, each of the substrates having a circuit chip with chip pads positioned therein and an electrically conductive feed-through line extending therethrough from a first surface of the substrate to a second surface of the substrate, the first surface being perpendicular to the second surface, each of the module interconnection layers being situated over a respective first surface of each of the substrates and comprising a module dielectric layer having module vias therein and a module pattern of electrical conductors extending through the module vias to couple the selected chip pads to the feed-through line; stacking the plurality of substrates; and applying a side interconnection layer over a side surface including the second surfaces of the substrates, the side interconnection layer comprising a side dielectric layer having side vias therein aligned with predetermined ones of the feed-through lines and a side pattern of electrical conductors extending through the side vias.
Claim 3
Dependent Claim
32 words
The method of claim 1, further including the step of, after stacking the plurality of substrates having module interconnect layers and prior to applying the side interconnection layer, planarizing the side surface.
Claim 4
Dependent Claim
9 words
The method of claim 2, wherein planarizing comprises grinding.
Claim 5
Dependent Claim
41 words
The method of claim 1, further including the step of, prior to stacking the plurality of substrates having module interconnect layers, cutting each of the plurality of substrates to expose a respective feed-through line and thereby form a respective second surface.
Claim 6
Dependent Claim
28 words
The method of claim 1, wherein the step of stacking the plurality of substrates having module interconnect layers includes applying adhesive between adjacent substrates having module interconnect layers.
Claim 7
Dependent Claim
28 words
The method of claim 1, further including, after stacking the plurality of substrates having module interconnect layers, inserting rods in the stack for holding the substrates in position.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-18 | 2001-02-17 | 2001-08-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-18 | 2005-02-17 | 2005-08-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-18 | 2009-02-17 | 2009-08-19 | $7700.00 | Window Closed / Lapsed |