Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
140 words
In an integrated circuit, a two-pin diagnostic data port comprising: a processor data bus; a processor address bus; serially connected memory connected to said processor data bus and said processor address bus, and said serially connected memory having a serial clock terminal and a serial output terminal wherein data are written into said serially connected memory using said processor data and address busses; and said data are serially provided to said serial output terminal in response to a clock signal on said serial clock terminal; a first output pin coupled to a clock signal that is supplied to said serial clock terminal wherein said first pin is a first pin of said two-pin diagnostic port; and a second output pin coupled to said serial output terminal wherein said second output pin is a second pin of said two-pin diagnostic port.
Claim 2
Dependent Claim
140 words
In an integrated circuit, a two-pin diagnostic data port comprising: a processor data bus; a processor address bus; serially connected memory connected to said processor data bus and said processor address bus, and said serially connected memory having a serial clock terminal and a serial output terminal wherein data are written into said serially connected memory using said processor data and address busses; and said data are serially provided to said serial output terminal in response to a clock signal on said serial clock terminal; a first output pin coupled to a clock signal that is supplied to said serial clock terminal wherein said first pin is a first pin of said two-pin diagnostic port; and a second output pin coupled to said serial output terminal wherein said second output pin is a second pin of said two-pin diagnostic port.
Claim 3
Dependent Claim
60 words
In an integrated circuit, the two-pin diagnostic data port of claim 1 further comprising: a control register coupled to said serially connected memory and coupled to said processor data and address busses wherein upon writing to said control register, said clock signal is applied to said serial clock terminal of said serially connected memory and to said first output pin.
Claim 4
Dependent Claim
30 words
In an integrated circuit, the two-pin diagnostic data port of claim 1 further comprising: a clock input line coupled to said serial clock terminal and to said first output pin.
Claim 5
Dependent Claim
25 words
In an integrated circuit, a two-pin diagnostic data port as in claim 1 wherein said serially connected memory comprises a plurality of serially connected registers.
Claim 6
Dependent Claim
27 words
In an integrated circuit, a two-pin diagnostic data port as in claim 4 wherein said plurality of serially connected registers comprises three serially connected sixteen bit registers.
Claim 7
Dependent Claim
36 words
In an integrated circuit, a two-pin diagnostic data port as in claim 3 wherein said serially connected memory further comprises a shift terminal, and further wherein said clock input line is coupled to said shift terminal.
Claim 8
Dependent Claim
87 words
In an integrated circuit, a two-pin diagnostic data port as in claim 1 further comprising: an address decoder circuit coupled to: said processor data bus; said processor address bus; and said serially connected memory wherein, upon receiving a write sequence of signals from processor, said address decoder circuit loads data from said processor data bus into said serially connected memory, and upon receiving a read sequence of signals from said processor, said address decoder circuit transfers data from said serially connected memory to said processor data bus.
Claim 9
Dependent Claim
25 words
In an integrated circuit, a two-pin diagnostic data port as in claim 7, wherein said serially connected memory comprises a plurality of serially connected registers.