Method of manufacturing a crown shaped capacitor with horizontal fins for high density DRAMs

Claim 1

A method for manufacturing an integrated circuit capacitor, the method comprising the steps of: forming a first conductive layer on a semiconductor substrate; forming a composition layer on said first conductive layer, said composition layer consisting of alternating BPSG layers and silicon dioxide layers; forming a photoresist mask pattern atop said composition layer; removing said first conductive layer and said composition layer not protected by said photoresist mask pattern; selectively etching said BPSG layers and said silicon dioxide layers by using low pressure HF vapor, the relative susceptibility to etching of said BPSG layers to said silicon dioxide layers being about 2000 to 1; forming a second conductive layer on said substrate and over said composition layer; forming spacers from said second conductive layer on the sides of said composition layer; removing said composition layer by using a buffer oxide etching; forming a dielectric film on the surface of said first conductive layer and said second conductive layer; and forming a third conductive layer over said dielectric film.

Claim 2

A method for manufacturing an integrated circuit capacitor, the method comprising the steps of: forming a first conductive layer on a semiconductor substrate; forming a composition layer on said first conductive layer, said composition layer consisting of alternating BPSG layers and silicon dioxide layers; forming a photoresist mask pattern atop said composition layer; removing said first conductive layer and said composition layer not protected by said photoresist mask pattern; selectively etching said BPSG layers and said silicon dioxide layers by using low pressure HF vapor, the relative susceptibility to etching of said BPSG layers to said silicon dioxide layers being about 2000 to 1; forming a second conductive layer on said substrate and over said composition layer; forming spacers from said second conductive layer on the sides of said composition layer; removing said composition layer by using a buffer oxide etching; forming a dielectric film on the surface of said first conductive layer and said second conductive layer; and forming a third conductive layer over said dielectric film.

Claim 14

A method for manufacturing an integrated circuit capacitor, the method comprising the steps of: forming a first conductive layer on a semiconductor substrate; forming on said first conductive layer a composition layer that consists of alternating sublayers of BPSG sublayers and silicon dioxide sublayers; forming a photoresist mask pattern on said composition layer; removing said first conductive layer and said composition layer not covered by said photoresist mask pattern; using highly selective etching to remove a portion of said BPSG sublayers and said silicon dioxide sublayers by using low pressure HF vapor, the relative susceptibility to etching of said BPSG sublayers to said silicon dioxide sublayers being about 2000 to 1; forming a second conductive layer on said substrate and over said composition layer; etching said second conductive layer to form spacers on the sides of said composition layer by anisotropically etching back said second conductive layer; removing said composition layer by using a buffer oxide etchant; forming a dielectric film on the surface of said first conductive layer and said second conductive layer; and forming a third conductive layer over said dielectric film.

Claim 15

A method for manufacturing an integrated circuit capacitor, the method comprising the steps of: forming a first conductive layer on a semiconductor substrate; forming on said first conductive layer a composition layer that consists of alternating sublayers of BPSG sublayers and silicon dioxide sublayers; forming a photoresist mask pattern on said composition layer; removing said first conductive layer and said composition layer not covered by said photoresist mask pattern; using highly selective etching to remove a portion of said BPSG sublayers and said silicon dioxide sublayers by using low pressure HF vapor, the relative susceptibility to etching of said BPSG sublayers to said silicon dioxide sublayers being about 2000 to 1; forming a second conductive layer on said substrate and over said composition layer; etching said second conductive layer to form spacers on the sides of said composition layer by anisotropically etching back said second conductive layer; removing said composition layer by using a buffer oxide etchant; forming a dielectric film on the surface of said first conductive layer and said second conductive layer; and forming a third conductive layer over said dielectric film.

Claim 16

A method of forming a horizontal polysilicon fin comprising the steps of: forming a first polysilicon layer; forming a composition layer that consists of alternating BPSG layers and silicon dioxide layers on said first polysilicon layer; forming a photoresist mask pattern on said composition layer; removing said first polysilicon layer and said BPSG layers and said silicon dioxide layers not covered by said first photoresist mask pattern; removing said photoresist; using high selective etching to remove a portion of said BPSG layers and said silicon dioxide layers by using low pressure HF vapor, the relative susceptibility to etching of said BPSG layers to said silicon dioxide layers being about 2000 to 1; forming a second polysilicon layer on said substrate and over said composition layer; forming spacers on the sides of said composition layer by anisotropically etching back said second polysilicon layer; and removing said composition layer by using a buffer oxide etchant.

Claim 17

A method of forming a horizontal polysilicon fin comprising the steps of: forming a first polysilicon layer; forming a composition layer that consists of alternating BPSG layers and silicon dioxide layers on said first polysilicon layer; forming a photoresist mask pattern on said composition layer; removing said first polysilicon layer and said BPSG layers and said silicon dioxide layers not covered by said first photoresist mask pattern; removing said photoresist; using high selective etching to remove a portion of said BPSG layers and said silicon dioxide layers by using low pressure HF vapor, the relative susceptibility to etching of said BPSG layers to said silicon dioxide layers being about 2000 to 1; forming a second polysilicon layer on said substrate and over said composition layer; forming spacers on the sides of said composition layer by anisotropically etching back said second polysilicon layer; and removing said composition layer by using a buffer oxide etchant.