US5543346A
Expired / Lapsed
US
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Method of fabricating a dynamic random access memory stacked capacitor
Assignee: SK Hynix Inc
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Filing: 1994-08-30
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Granted: 1996-08-06
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Expires: 2014-08-30
Abstract
Abstract A DRAM capacitor and a method for fabricating the same, capable of achieving an increase in surface area and thereby an increase in capacitance while reducing the topology, by simply forming a conduction layer, as a charge storage electrode, comprised of conduction spacers around a double-layer pin-shaped conduction layer pattern or a combination of a central conduction layer pattern and an outer conduction layer pattern having an upwardly-opened dome structure surrounding the central conduction layer pattern, using an etch rate difference between insulating films.
Inventors
- 👤 Dong Y. Keum
- 👤 Cheol S. Park
- 👤 Eui K. Ryou
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 08:33
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/31; H10B12/318
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
426 words
A method for fabricating dynamic random access memory capacitor, comprising the steps of: forming a planarizing layer over a semiconductor substrate including a field oxide film, a gate oxide film, gates, and bit lines; forming a first insulating film layer over the planarizing layer; forming a first conduction layer over the first insulating film layer; forming a second insulating film layer over the first conduction layer; sequentially removing portions of the layers from the second insulating film layer to the planarizing layer such that an active region of the semiconductor substrate to be in contact with the capacitor is exposed, thereby forming a contact hole; forming a second conduction layer over an entire exposed upper surface of the resulting structure after forming said contact hole to cover an upper surface of second insulating film and fill the contact hole; forming a third insulating film layer over the second conduction layer; forming a fourth insulating film layer over the third insulating film, the fourth insulating film being made of a different material from that of the third insulating film; forming a fifth insulating film over the fourth insulating film, the fifth insulating film being made of a different material from that of the fourth insulating film; sequentially removing the layers from the fifth insulating film to the second insulating film except for their portions to constitute a part of the capacitor, thereby forming stacked patterns consisting of fifth insulating film, fourth insulating film, third insulating film, second conduction layer, second insulating film and contact hole; forming a sixth insulating film over said stacked patterns, the sixth insulating film being made of a different material from that of the fifth insulating film; etching the sixth insulating film at its entire upper surface, thereby forming insulating spacers on side walls of the second insulating film, second conduction layer and third insulating film; partially removing the fourth insulating film except for its portion disposed above the contact hole, thereby forming a gap between the third and fifth insulating film after forming said insulating spacers; coating a conduction material over an entire exposed surface of the resulting structure after forming said gap, thereby forming a third conduction layer covering an upper surface of the first conduction layer and filling the gap; etching the third conduction layer at its entire upper surface such that the third conduction layer remains at its portion disposed in the gap and on the insulating spacers; and removing an exposed portion of the first conduction layer using the stacked patterns as a mask, thereby isolating said capacitor.
Claim 2
Independent Claim
426 words
A method for fabricating dynamic random access memory capacitor, comprising the steps of: forming a planarizing layer over a semiconductor substrate including a field oxide film, a gate oxide film, gates, and bit lines; forming a first insulating film layer over the planarizing layer; forming a first conduction layer over the first insulating film layer; forming a second insulating film layer over the first conduction layer; sequentially removing portions of the layers from the second insulating film layer to the planarizing layer such that an active region of the semiconductor substrate to be in contact with the capacitor is exposed, thereby forming a contact hole; forming a second conduction layer over an entire exposed upper surface of the resulting structure after forming said contact hole to cover an upper surface of second insulating film and fill the contact hole; forming a third insulating film layer over the second conduction layer; forming a fourth insulating film layer over the third insulating film, the fourth insulating film being made of a different material from that of the third insulating film; forming a fifth insulating film over the fourth insulating film, the fifth insulating film being made of a different material from that of the fourth insulating film; sequentially removing the layers from the fifth insulating film to the second insulating film except for their portions to constitute a part of the capacitor, thereby forming stacked patterns consisting of fifth insulating film, fourth insulating film, third insulating film, second conduction layer, second insulating film and contact hole; forming a sixth insulating film over said stacked patterns, the sixth insulating film being made of a different material from that of the fifth insulating film; etching the sixth insulating film at its entire upper surface, thereby forming insulating spacers on side walls of the second insulating film, second conduction layer and third insulating film; partially removing the fourth insulating film except for its portion disposed above the contact hole, thereby forming a gap between the third and fifth insulating film after forming said insulating spacers; coating a conduction material over an entire exposed surface of the resulting structure after forming said gap, thereby forming a third conduction layer covering an upper surface of the first conduction layer and filling the gap; etching the third conduction layer at its entire upper surface such that the third conduction layer remains at its portion disposed in the gap and on the insulating spacers; and removing an exposed portion of the first conduction layer using the stacked patterns as a mask, thereby isolating said capacitor.
Claim 3
Dependent Claim
30 words
A method in accordance with claim 1, wherein the planarizing layer is made of a material exhibiting a high wet etch selectivity to the first, second and third insulating films.
Claim 4
Dependent Claim
39 words
A method in accordance with claim 1, wherein the planarizing layer is made of a combination of a boro phospho silicate glass, a phospho silicate glass, a tetraethylorthosilicate or a combination of an oxide film and a nitride film.
Claim 5
Dependent Claim
39 words
A method in accordance with claim 2, wherein the planarizing layer is made of a combination of a boro phospho silicate glass, a phospho silicate glass, a tetraethylorthosilicate or a combination of an oxide film and a nitride film.
References Cited (Backward Citations)
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| 3.5 Years (Year 4) | 1999-08-06 | 2000-02-05 | 2000-08-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-06 | 2004-02-05 | 2004-08-06 | $3760.00 | Window Closed / Lapsed |
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