Patent US5656514A successfully refreshed from Google Patents.
US5656514A
Expired / Lapsed
US
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Method for making heterojunction bipolar transistor with self-aligned retrograde emitter profile
Assignee: GlobalFoundries Inc
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Filing: 1994-11-22
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Granted: 1997-08-12
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Expires: 2014-11-22
Abstract
Abstract A high gain, high frequency transistor is formed having a combination of a moderately doped retrograde emitter and a collector which is formed by self-aligned implantation through an emitter opening window. This combination allows continued base width scaling and ensures high current capability yet limits the electric field at the emitter-base junction, particularly near the base contacts, in order to reduce leakage and capacitance and to enhance breakdown voltage. Cut-off frequencies on the order of 100 GHz can thus be obtained in the performance of a transistor with a 30 nm base width in a SiGe device.
Inventors
- 👤 David Ahlgren
- 👤 Jack Chu
- 👤 Martin Revitz
- 👤 Paul Ronsheim
- 👤 Mary Saccamango
- 👤 David Sunderland
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 05:21
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/021; Y; Y10; Y10S; Y10S438/00; Y10S438/936
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
104 words
A method of making a transistor structure including an emitter-base heterojunction and a retrograde emitter including the steps of depositing a layer over a collector region, said layer including an emitter-base heterojunction having a concentration profile of at least one band gap determining alloying material, said step of depositing a layer including the step of depositing impurities in said layer in accordance with an impurity concentration profile, forming an emitter opening in an insulator over said layer including said emitter-base heterojunction, and forming an emitter of said transistor structure by impurity implantation in said layer including said emitter-base heterojunction self-aligned with said emitter opening.
Claim 2
Independent Claim
104 words
A method of making a transistor structure including an emitter-base heterojunction and a retrograde emitter including the steps of depositing a layer over a collector region, said layer including an emitter-base heterojunction having a concentration profile of at least one band gap determining alloying material, said step of depositing a layer including the step of depositing impurities in said layer in accordance with an impurity concentration profile, forming an emitter opening in an insulator over said layer including said emitter-base heterojunction, and forming an emitter of said transistor structure by impurity implantation in said layer including said emitter-base heterojunction self-aligned with said emitter opening.
Claim 3
Dependent Claim
25 words
A method as recited in claim 1, including the further step of forming a gradually varying alloy composition effective to produce an accelerating quasi-electric field.
Claim 4
Dependent Claim
29 words
A method as recited in claim 1, wherein said depositing impurities step includes the further step of forming a collector region by impurity implantation self-aligned with said emitter opening.
Claim 5
Dependent Claim
24 words
A method recited in claim 1, wherein said layer including said emitter-base heterojunction is composed primarily of silicon and said alloying material is germanium.
Claim 6
Dependent Claim
43 words
A method recited in claim 1, wherein said process includes the further steps of forming a deposit of heavily doped polysilicon to said layer including said emitter-base heterojunction, and diffusing impurities from said heavily doped polysilicon into said layer including said emitter-base heterojunction.
Claim 7
Dependent Claim
36 words
A method as recited in claim 1, including the further steps of implanting impurities to a shallow depth in said layer including said emitter-base heterojunction and depositing a layer of metal to form an emitter contact.
Claim 8
Dependent Claim
31 words
A method as recited in claim 2, including the further steps of forming a deposit of heavily doped polysilicon to said layer including said emitter-base heterojunction to form an emitter contact.
Claim 9
Dependent Claim
28 words
A method as recited in claim 7, wherein said layer including said emitter base heterojunction is composed primarily of silicon and said band gap determining material is germanium.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-11 | 2001-02-10 | 2001-08-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-11 | 2005-02-10 | 2005-08-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-11 | 2009-02-10 | 2009-08-12 | $7700.00 | Window Closed / Lapsed |