Patent US5654240A successfully refreshed from Google Patents.
US5654240A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit fabrication having contact opening
Assignee: Nokia of America Corp
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Filing: 1996-04-12
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Granted: 1997-08-05
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Expires: 2016-04-12
Abstract
Abstract A method of semiconductor fabrication having applicability to forming contacts to sources and drains especially in SRAM applications is disclosed. A dielectric and an overlying polysilicon conductor are formed and patterned thereby exposing a semiconductor substrate. A silicide layer is deposited, thereby contacting the polysilicon layer and the substrate. Subsequent patterning of the silicide layer using an oxide hard mask provides electrical contact between the polysilicon layer and the substrate without the risk of trenching into the substrate.
Inventors
- 👤 Kuo-Hua Lee
- 👤 Chen-Hua Douglas Yu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:42
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/064; H10W20/066; H10D; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10D64/0113
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
126 words
A method of semiconductor integrated circuit fabrication comprising: forming a patterned dielectric over a substrate, said patterned dielectric exposing a portion of said substrate; forming a patterned first conductor over said patterned dielectric, said patterned first conductor not contacting said substrate; said patterned first conductor having a top and a side; forming a second conductor layer contacting the said top and side of said first conductor; and contacting said substrate; forming a material layer over said second conductor; patterning said material layer, thereby creating an edge of said material layer and exposing a portion of said second conductor layer; and etching the exposed portion of said second conductor layer, thereby removing at least a portion of said second conductor which was over said patterned first conductor.
Claim 2
Independent Claim
126 words
A method of semiconductor integrated circuit fabrication comprising: forming a patterned dielectric over a substrate, said patterned dielectric exposing a portion of said substrate; forming a patterned first conductor over said patterned dielectric, said patterned first conductor not contacting said substrate; said patterned first conductor having a top and a side; forming a second conductor layer contacting the said top and side of said first conductor; and contacting said substrate; forming a material layer over said second conductor; patterning said material layer, thereby creating an edge of said material layer and exposing a portion of said second conductor layer; and etching the exposed portion of said second conductor layer, thereby removing at least a portion of said second conductor which was over said patterned first conductor.
Claim 3
Dependent Claim
12 words
The method of claim 1 in which said first conductor is polysilicon.
Claim 4
Dependent Claim
15 words
The method of claim 1 in which said second conductor is a refractory metal silicide.
Claim 5
Dependent Claim
14 words
The method of claim 3 in which said refractory metal silicide is tungsten silicide.
Claim 6
Dependent Claim
13 words
The method of claim 1 in which said material layer is silicon dioxide.
Claim 7
Dependent Claim
14 words
The method of claim 5 in which said silicon dioxide is formed from TEOS.
Claim 8
Dependent Claim
26 words
The method of claim 1 in which said step of patterning said material layer creates an edge which overlies the previously exposed portion of said substrate.
Claim 9
Dependent Claim
100 words
The method of claim 7 in which said second conductor has a first portion which has a first thickness measured perpendicular from the substrate surface which covers a substantial portion of the previously exposed portion of said substrate and said second conductor has a second portion which has a second thickness measured perpendicular from said substrate surface said second thickness being greater than said first thickness, said second portion being adjacent said patterned dielectric and said patterned first conductor, and in which said edge of said material layer overlies said second portion of said second conductor having said second thickness.
Claim 10
Dependent Claim
29 words
The method of claim 1 in which said step of patterning said material layer creates said edge which is not vertically above the previously exposed portion of the substrate.
Claim 11
Dependent Claim
14 words
The method of claim 8 further including the steps of removing said material layer.
Claim 12
Dependent Claim
43 words
The method of claim 10 in which a portion of said first patterned conductor layer is exposed during the said etching of the exposed portion of the said second conductor layer and said portion of said first patterned conductor layer is subsequently removed.
Claim 13
Dependent Claim
102 words
The method of claim 7 in which said second conductor has a first portion which has a first thickness measured perpendicular from the substrate surface said first thickness covering a substantial portion of the previously exposed portion of said substrate and said second conductor has a second portion which has a second thickness measured perpendicular from said substrate surface said second thickness being greater than said first thickness, said second portion being adjacent said patterned dielectric and said patterned first conductor, and in which said edge of said material layer overlies said first portion of said second conductor having said first thickness.
Claim 14
Dependent Claim
14 words
The method of claim 12 further including the step of removing said material layer.
References Cited (Backward Citations)
US4288256A
Cited
US4373251A
Cited
US4994402A
Cited
US5013686A
Cited
US5210048A
Cited
US5110753A
Cited
US5162262A
Cited
US4978637A
Cited
US5151387A
Cited
US5124280A
Cited
US5256584A
Cited
US5149665A
Cited
US5270240A
Cited
US5256248A
Cited
US5246883A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-04 | 2001-02-03 | 2001-08-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-04 | 2005-02-03 | 2005-08-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-04 | 2009-02-03 | 2009-08-05 | $7700.00 | Window Closed / Lapsed |