US5270240A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Four poly EPROM process and structure comprising a conductive source line structure and self-aligned polycrystalline silicon digit lines
Assignee: Round Rock Research LLC
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Filing: 1992-09-09
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Granted: 1993-12-14
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Expires: 2012-09-09
Abstract
Abstract A process and structure for an electrically erasable programmable read-only memory is described. The PROM is manufactured with four poly layers, the poly layers forming the floating and control gates, a structure coupling isolated source areas, and the fourth layer forming the digit lines. The inventive structure allows for a self-aligned poly source line which removes the need for an etch of the field oxide which is required in conventional EEPROM designs, which are known to be difficult to control. The poly digit line is also self-aligned and has a large margin of misalignment error in an etch to expose the drain region of the substrate.
Inventors
- 👤 Roger R. Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 19:13
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; H10B69/00
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
244 words
A process forming a semiconductor memory device, comprising the steps of: a) forming a first insulation layer over a substrate, said first insulation layer comprising alternating rows of field and gate insulation; b) forming a first conductive layer over said first insulation layer, said first conductive layer comprising conductive rows overlying and parallel with said gate insulation; c) forming a second insulation layer over said first conductive layer; d) forming a second conductive layer over said second insulation layer; e) removing portions of said second conductive layer to form word lines which are perpendicular with said field insulation; f) removing portions of said conductive rows to form floating gates at the junctions of said word lines and said gate insulation; g) removing portions of said gate insulation which are not protected by said word lines thereby forming areas of exposed substrate segmented in the row direction by said gate insulation and in the column direction by said field insulation; h) changing the electrical properties of said exposed substrate areas to form source and drain regions; i) forming a third insulation layer over said second conductive layer; j) forming a third conductive layer, said third conductive layer forming conductive source lines, each source line coupling a column of source regions; k) forming a fourth insulation layer over said third conductive layer; and l) forming a fourth conductive layer, said fourth conductive layer forming conductive digit lines, each digit line coupling a row of drain regions.
Claim 2
Dependent Claim
244 words
A process forming a semiconductor memory device, comprising the steps of: a) forming a first insulation layer over a substrate, said first insulation layer comprising alternating rows of field and gate insulation; b) forming a first conductive layer over said first insulation layer, said first conductive layer comprising conductive rows overlying and parallel with said gate insulation; c) forming a second insulation layer over said first conductive layer; d) forming a second conductive layer over said second insulation layer; e) removing portions of said second conductive layer to form word lines which are perpendicular with said field insulation; f) removing portions of said conductive rows to form floating gates at the junctions of said word lines and said gate insulation; g) removing portions of said gate insulation which are not protected by said word lines thereby forming areas of exposed substrate segmented in the row direction by said gate insulation and in the column direction by said field insulation; h) changing the electrical properties of said exposed substrate areas to form source and drain regions; i) forming a third insulation layer over said second conductive layer; j) forming a third conductive layer, said third conductive layer forming conductive source lines, each source line coupling a column of source regions; k) forming a fourth insulation layer over said third conductive layer; and l) forming a fourth conductive layer, said fourth conductive layer forming conductive digit lines, each digit line coupling a row of drain regions.
Claim 3
Dependent Claim
12 words
The method of claim 1 wherein said fourth conductive layer comprises silicon.
Claim 4
Dependent Claim
17 words
The method of claim 1 wherein said first, second, third, and fourth conductive layers comprise polycrystalline silicon.
Claim 5
Dependent Claim
32 words
The method of claim 1 further comprising an etch step after said step k) wherein said etch step exposes said drain regions and allows for self-aligned buried contacts to said drain regions.
Claim 6
Dependent Claim
32 words
The method of claim 1 further comprising an etch step after said step i) wherein said etch step exposes said source regions and allows for self-aligned buried contacts to said source regions.
Claim 7
Dependent Claim
17 words
The method of claim 1 wherein steps e), f), and g) are performed during a single etch.
Claim 8
Dependent Claim
13 words
The method of claim 1 wherein said changing step is accomplished by doping.
Claim 9
Dependent Claim
11 words
The method of claim 1 wherein said insulation layers comprise oxide.
Claim 10
Dependent Claim
14 words
The method of claim 1 wherein said second insulation layer comprises oxide and nitride.
Claim 11
Dependent Claim
38 words
The method of claim 1, further comprising the step of forming a fifth conductive layer over said fourth conductive layer and contacting said fourth conductive layer, said fifth conductive layer being more conductive than said fourth conductive layer.
Claim 12
Dependent Claim
12 words
The method of claim 10 wherein said fifth conductive layer comprises titanium.
Claim 13
Independent Claim
248 words
A method of forming a programmable read-only memory device, comprising the steps of: a) forming a first insulation layer over a substrate, said first insulation layer comprising alternating rows of field oxide and gate oxide; b) forming a first conductive layer over said first insulation layer, said first conductive layer comprising conductive rows overlying and parallel with said gate oxide; c) forming a second insulation layer over said first conductive layer; d) forming a second conductive layer over said second insulation layer; e) removing portions of said second conductive layer to form control gates which are perpendicular with said rows of field oxide; f) removing portions of said first conductive layer to form floating gates at the junctions of said control gates and said gate oxide rows; g) removing portions of said gate oxide rows which are not protected by said control gates thereby forming areas of exposed substrate segmented in the row direction by gate oxide and in the column direction by field oxide; h) doping of said exposed substrate areas to form transistor source and drain regions; i) forming a third insulation layer over said second conductive layer; j) forming a third conductive layer, said third conductive layer forming conductive source lines, each source line coupling a column of source regions; k) forming a fourth insulation layer over said third conductive layer; and l) forming a fourth conductive layer, said fourth conductive layer forming conductive digit lines, each digit line coupling a row of drain regions.
Claim 14
Independent Claim
248 words
A method of forming a programmable read-only memory device, comprising the steps of: a) forming a first insulation layer over a substrate, said first insulation layer comprising alternating rows of field oxide and gate oxide; b) forming a first conductive layer over said first insulation layer, said first conductive layer comprising conductive rows overlying and parallel with said gate oxide; c) forming a second insulation layer over said first conductive layer; d) forming a second conductive layer over said second insulation layer; e) removing portions of said second conductive layer to form control gates which are perpendicular with said rows of field oxide; f) removing portions of said first conductive layer to form floating gates at the junctions of said control gates and said gate oxide rows; g) removing portions of said gate oxide rows which are not protected by said control gates thereby forming areas of exposed substrate segmented in the row direction by gate oxide and in the column direction by field oxide; h) doping of said exposed substrate areas to form transistor source and drain regions; i) forming a third insulation layer over said second conductive layer; j) forming a third conductive layer, said third conductive layer forming conductive source lines, each source line coupling a column of source regions; k) forming a fourth insulation layer over said third conductive layer; and l) forming a fourth conductive layer, said fourth conductive layer forming conductive digit lines, each digit line coupling a row of drain regions.
Claim 15
Dependent Claim
12 words
The method of claim 12 wherein said fourth conductive layer comprises silicon.
Claim 16
Dependent Claim
17 words
The method of claim 12 wherein said first, second, third, and fourth conductive layers comprise polycrystalline silicon.
Claim 17
Dependent Claim
17 words
The method of claim 12 wherein steps e), f), and g) are performed during a single etch.
Claim 18
Dependent Claim
11 words
The method of claim 12 wherein said insulation layers comprise oxide.
Claim 19
Dependent Claim
14 words
The method of claim 12 wherein said second insulation layer comprises oxide and nitride.
Claim 20
Dependent Claim
32 words
The method of claim 12 further comprising an etch step after said step k) wherein said etch step exposes said drain regions and allows for self-aligned buried contacts to said drain regions.
Claim 21
Dependent Claim
32 words
The method of claim 12 further comprising an etch step after said step i) wherein said etch step exposes said source regions and allows for self-aligned buried contacts to said source regions.
Claim 22
Dependent Claim
38 words
The method of claim 12, further comprising the step of forming a fifth conductive layer over said fourth conductive layer and contacting said fourth conductive layer, said fifth conductive layer being more conductive than said fourth conductive layer.
Claim 23
Dependent Claim
12 words
The method of claim 12 wherein said fifth conductive layer comprises titanium.
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