Method of making large-scale EPROM memory with a checker board pattern and an improved coupling factor

Claim 1

A method for manufacturing a memory comprising floating gate MOS transistors arranged according to rows and columns on a substrate of a first conductivity type, each memory point of the memory comprising a pair of transistors arranged according to a row, said method comprising the following steps: depositing and etching a first polysilicon layer on the substrate to form, according to columns, strips in which the floating gates (23) of the transistors will be formed, implanting a dopant of a second conductivity type in the substrate by using the first polysilicon layer as a mask to form alternate drawing (21) and source (22) columns of said transistors, forming isolation strips (2a) between the stripes of the first polysilicon layer, depositing a second polysilicon layer (25) and isolating its upper surfaces (26), etching the second polysilicon layer (25) to cover, according to columns, the pairs of adjacent stripes from which will be formed the transistor floating gates of a transistor pair, isolating the lateral surfaces (27) of the second polysilicon layer, depositing a third polysilicon layer (28), etching by a same mask, according to rows, the three polysilicon layers, forming an isolating layer, and establishing contacts with remaining stripes of the third polysilicon level (word lines), with the drain columns (bit lines) and with the source columns.

Claim 2

A method for manufacturing a memory comprising floating gate MOS transistors arranged according to rows and columns on a substrate of a first conductivity type, each memory point of the memory comprising a pair of transistors arranged according to a row, said method comprising the following steps: depositing and etching a first polysilicon layer on the substrate to form, according to columns, strips in which the floating gates (23) of the transistors will be formed, implanting a dopant of a second conductivity type in the substrate by using the first polysilicon layer as a mask to form alternate drawing (21) and source (22) columns of said transistors, forming isolation strips (2a) between the stripes of the first polysilicon layer, depositing a second polysilicon layer (25) and isolating its upper surfaces (26), etching the second polysilicon layer (25) to cover, according to columns, the pairs of adjacent stripes from which will be formed the transistor floating gates of a transistor pair, isolating the lateral surfaces (27) of the second polysilicon layer, depositing a third polysilicon layer (28), etching by a same mask, according to rows, the three polysilicon layers, forming an isolating layer, and establishing contacts with remaining stripes of the third polysilicon level (word lines), with the drain columns (bit lines) and with the source columns.