US4978637A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Local interconnect process for integrated circuits
Assignee: STMicroelectronics lnc USA
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Filing: 1989-05-31
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Granted: 1990-12-18
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Expires: 2009-05-31
Abstract
Abstract A silicide layer, to improve conductivity, is formed over a first layer of polycrystalline silicon, followed by a second layer of polycrystalline silicon. This structure is then patterned to form gate regions over active areas. A layer of metal silicide is formed over the entire surface of the chip, and patterned to form local interconnect. Etching of the second metal silicide layer is stopped by the second polycrystalline silicon layer, thereby protecting the first metal silicide layer from damage.
Inventors
- 👤 Fu-Tai Liou
- 👤 Yih-Shung Lin
- 👤 Fusen E. Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:11
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10P; H10P32/00; H10P32/30; H10P32/302; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/0698; H10W20/40; H10W20/41; H10W20/44; H10W20/4451; Y; Y10; Y10S; Y10S148/00; Y10S148/015; Y10S148/019; Y10S148/02
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
162 words
A method for forming electrical interconnections in an integrated circuit, comprising the steps of: forming a gate oxide layer on a substrate; forming a gate polycrystalline silicon layer over the gate oxide layer; forming a first conductive layer including metal over the gate polycrystalline silicon layer; forming a conductive cap layer over the first conductive layer including metal; patterning the gate oxide, gate polycrystalline silicon, first conductive layer including metal, and conductive cap layers to form gates over active regions in the substrate; forming sidewall insulating regions on the gates; forming a second conductive layer including metal over the integrated circuit; and patterning the second conductive layer including metal to form electrical interconnections, wherein the conductive cap layer protects the first conductive layer from damage during such patterning step and wherein the second conductive layer makes electrical contact with the gates through the conductive cap layer, whereby electrical connections are made between the gates and the substrate through the second conductive layer.
Claim 2
Independent Claim
162 words
A method for forming electrical interconnections in an integrated circuit, comprising the steps of: forming a gate oxide layer on a substrate; forming a gate polycrystalline silicon layer over the gate oxide layer; forming a first conductive layer including metal over the gate polycrystalline silicon layer; forming a conductive cap layer over the first conductive layer including metal; patterning the gate oxide, gate polycrystalline silicon, first conductive layer including metal, and conductive cap layers to form gates over active regions in the substrate; forming sidewall insulating regions on the gates; forming a second conductive layer including metal over the integrated circuit; and patterning the second conductive layer including metal to form electrical interconnections, wherein the conductive cap layer protects the first conductive layer from damage during such patterning step and wherein the second conductive layer makes electrical contact with the gates through the conductive cap layer, whereby electrical connections are made between the gates and the substrate through the second conductive layer.
Claim 3
Dependent Claim
21 words
The method of claim 1 wherein the first and second conducive layers including metal are formed from the same conductive material.
Claim 4
Dependent Claim
13 words
The method of claim 2, wherein the conductive material is a refractory metal.
Claim 5
Dependent Claim
14 words
The method of claim 2, wherein the conductive material is a refractory metal silicide.
Claim 6
Dependent Claim
13 words
The method of claim 4, wherein the refractory metal silicide is tantalum disilicide.
Claim 7
Dependent Claim
15 words
The method of claim 1, wherein the conductive cap layer is formed from polycrystalline silicon.
Claim 8
Dependent Claim
34 words
The method of claim 6 further comprising the step of: after said conductive cap layer forming step, introducing impurities into the gate polycrystalline silicon layer and the conductive cap layer to improve their conductivity.
Claim 9
Dependent Claim
15 words
The method of claim 7, wherein the impurities are introduced by a single implant step.
Claim 10
Dependent Claim
11 words
The method of claim 7 wherein the introduced impurities comprise phosphorous.
References Cited (Backward Citations)
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US4470189A
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US4640738A
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US4740484A
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US4774204A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-12-17 | 1994-06-18 | 1994-12-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-12-17 | 1998-06-18 | 1998-12-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-12-17 | 2002-06-18 | 2002-12-18 | $7700.00 | Window Closed / Lapsed |