Semiconductor processing methods of forming stacked capacitors

Claim 2

A semiconductor processing method of forming a stacked capacitor on a semiconductor wafer, the method comprising the following steps: providing a first node for electrical connection with a capacitor plate; providing a second node; providing an underlying layer of insulating material atop the wafer; providing an etch stop layer of insulative material over the underlying insulating layer, the etch stop layer being different in composition from the insulating material of the underlying layer; providing an intermediate layer of insulating material over the etch stop layer, the insulating material of the intermediate layer being different in composition from the insulating material of the etch stop layer with the insulating material of the intermediate layer being selectively etchable relative to the insulating material of the etch stop layer; etching a capacitor contact opening through the intermediate, etch stop and underlying insulating layers to the first node; providing a capacitor storage node within the capacitor contact opening in electrical connection with the first node, the storage node having outer sidewall surfaces; etching the intermediate insulating layer selectively relative to the capacitor storage node and etch stop layer, and first using the etch stop layer as an etch stop during such etching to expose only a portion of the outer surfaces of the capacitor storage node sidewalls; providing a capacitor dielectric layer over the outer sidewall surfaces of the capacitor storage node; providing a cell electrically conductive layer over the capacitor dielectric layer, the cell layer having an outer surface; providing an overlying layer of insulating material above the cell layer; and etching a first opening over the second node through the overlying and cell layers, and secondly using the etch stop layer as an etch stop during such first opening etching, the first opening having sidewalls, the first opening sidewalls including an exposed edge of the cell layer.

Claim 3

A semiconductor processing method of forming a memory cell of claim 1 wherein the etch stop layer is provided to a thickness of from about 100 Angstroms to about 4000 Angstroms.

Claim 4

A semiconductor processing method of forming a memory cell of claim 1 wherein the overlying and underlying insulating layers constitute the same material.

Claim 5

A semiconductor processing method of forming a memory cell of claim 1 wherein the etch stop layer comprises nitride.

Claim 6

A semiconductor processing method of forming a memory cell of claim 1 wherein the etch stop layer comprises SiO 2 deposited by decomposition of tetraethylorthosilicate (TEOS), the underlying layer comprising SiO 2 of another form.

Claim 7

A semiconductor processing method of forming a memory cell of claim 1 wherein the overlying and underlying layers comprise oxide, and the etch stop layer comprises nitride.

Claim 8

A semiconductor processing method of forming a stacked capacitor on a semiconductor wafer, the method comprising the following steps: providing a first node for electrical connection with a capacitor plate; providing a second node; providing an underlying layer of insulating material atop the wafer; providing a combination etch stop and oxidation barrier insulative layer over the underlying insulating layer, the combination layer being different in composition from the insulating material of the underlying layer; providing an intermediate layer of insulating material over the combination layer, the insulating material of the intermediate layer being different in composition from the insulating material of the combination layer with the insulating material of the intermediate layer being selectively etchable relative to the insulating material of the combination layer; etching a capacitor contact opening through the intermediate, combination and underlying insulating layers to the first node; providing a capacitor storage node within the capacitor contact opening in electrical connection with the first node, the storage node having outer sidewall surfaces; etching the intermediate insulating layer selectively relative to the capacitor storage node and combination layer, and using the combination layer as an etch stop during such etching to expose only a portion of the outer surfaces of the capacitor storage node sidewalls; providing a capacitor dielectric layer over the outer sidewall surfaces of the capacitor storage node; providing a cell electrically conductive oxidizable material layer over the capacitor dielectric layer, the cell layer having an outer surface; providing an electrically insulative oxidation barrier layer over the cell layer; providing an overlying layer of insulating material above the oxidation barrier layer; etching a first opening over the second node through the overlying, oxidation barrier and cell layers using the combination layer as an etch stop during such first opening etching, the first opening having sidewalls, the first opening sidewalls including an exposed edge of the cell layer; exposing the wafer having the first opening to an oxidizing ambient to oxidize the cell layer exposed edge, the oxidation barrier layer during such oxidation exposure inhibiting oxidation of the outer surface of the cell layer, the combination layer during such oxidation exposure inhibiting oxidation of the capacitor storage node; etching the combination layer from within the first opening; etching the underlying layer from within the first opening to outwardly expose the second node for electrical contact; and plugging the first opening with electrically conductive material.

Claim 9

A semiconductor processing method of forming a stacked capacitor on a semiconductor wafer, the method comprising the following steps: providing a first node for electrical connection with a capacitor plate; providing a second node; providing an underlying layer of insulating material atop the wafer; providing a combination etch stop and oxidation barrier insulative layer over the underlying insulating layer, the combination layer being different in composition from the insulating material of the underlying layer; providing an intermediate layer of insulating material over the combination layer, the insulating material of the intermediate layer being different in composition from the insulating material of the combination layer with the insulating material of the intermediate layer being selectively etchable relative to the insulating material of the combination layer; etching a capacitor contact opening through the intermediate, combination and underlying insulating layers to the first node; providing a capacitor storage node within the capacitor contact opening in electrical connection with the first node, the storage node having outer sidewall surfaces; etching the intermediate insulating layer selectively relative to the capacitor storage node and combination layer, and using the combination layer as an etch stop during such etching to expose only a portion of the outer surfaces of the capacitor storage node sidewalls; providing a capacitor dielectric layer over the outer sidewall surfaces of the capacitor storage node; providing a cell electrically conductive oxidizable material layer over the capacitor dielectric layer, the cell layer having an outer surface; providing an electrically insulative oxidation barrier layer over the cell layer; providing an overlying layer of insulating material above the oxidation barrier layer; etching a first opening over the second node through the overlying, oxidation barrier and cell layers using the combination layer as an etch stop during such first opening etching, the first opening having sidewalls, the first opening sidewalls including an exposed edge of the cell layer; exposing the wafer having the first opening to an oxidizing ambient to oxidize the cell layer exposed edge, the oxidation barrier layer during such oxidation exposure inhibiting oxidation of the outer surface of the cell layer, the combination layer during such oxidation exposure inhibiting oxidation of the capacitor storage node; etching the combination layer from within the first opening; etching the underlying layer from within the first opening to outwardly expose the second node for electrical contact; and plugging the first opening with electrically conductive material.

Claim 10

A semiconductor processing method of forming a memory cell of claim 7 wherein the oxidation barrier layer thickness is at least about 150 Angstroms.

Claim 11

A semiconductor processing method of forming a memory cell of claim 7 wherein the oxidation barrier layer thickness is from about 250 Angstroms to about 1500 Angstroms.

Claim 12

A semiconductor processing method of forming a memory cell of claim 7 wherein the combination layer is provided to a thickness of from about 100 Angstroms to about 4000 Angstroms.

Claim 13

A semiconductor processing method of forming a memory cell of claim 7 wherein the overlying and underlying insulating layers constitute the same material.

Claim 14

A semiconductor processing method of forming a memory cell of claim 7 wherein the combination layer comprises nitride.

Claim 15

A semiconductor processing method of forming a memory cell of claim 7 wherein the combination layer comprises SiO 2 deposited by decomposition of tetraethylorthosilicate (TEOS), the underlying layer comprising SiO 2 of another form.

Claim 16

A semiconductor processing method of forming a memory cell of claim 7 wherein the overlying and underlying layers comprise oxide, and the combination layer comprises nitride.

Claim 17

A semiconductor processing method of forming a stacked capacitor on a semiconductor wafer, the method comprising the following steps: providing a first node for electrical connection with a capacitor plate; providing a second node; providing an underlying layer of insulating material atop the wafer; providing a combination etch stop and oxidation barrier insulative layer over the underlying insulating layer, the combination layer being different in composition from the insulating material of the underlying layer; providing an intermediate layer of insulating material over the combination layer, the insulating material of the intermediate layer being different in composition from the insulating material of the combination layer with the insulating material of the intermediate layer being selectively etchable relative to the insulating material of the combination layer; etching a capacitor contact opening through the intermediate, combination and underlying insulating layers to the first node; providing a capacitor storage node within the capacitor contact opening in electrical connection with the first node, the storage node having outer sidewall surfaces; etching the intermediate insulating layer selectively relative to the capacitor storage node and combination layer, and using the combination layer as an etch stop during such etching to expose only a portion of the outer surfaces of the capacitor storage node sidewalls; providing a capacitor dielectric layer over the outer sidewall surfaces of the capacitor storage node; providing a cell electrically conductive oxidizable material layer over the capacitor dielectric layer, the cell layer having an outer surface; providing an electrically insulative oxidation barrier layer over the cell layer; providing an overlying layer of insulating material above the oxidation barrier layer; providing a masking layer of the same material as the combination layer above the overlying layer, the masking layer being provided to a thickness which is greater than that of the combination layer; etching a first opening over the second node through the overlying, oxidation barrier and cell layers using the combination layer as an etch stop during such first opening etching, the first opening having sidewalls, the first opening sidewalls including an exposed edge of the cell layer; exposing the wafer having the first opening to an oxidizing ambient to oxidize the cell layer exposed edge, the oxidation barrier layer during such oxidation exposure inhibiting oxidation of the outer surface oft he cell layer, the combination layer during such oxidation exposure inhibiting oxidation of the capacitor storage node; etching the combination layer from within the first opening; etching the underlying layer from within the first opening to outwardly expose the second node for electrical contact; and plugging the first opening with electrically conductive material.

Claim 18

A semiconductor processing method of forming a stacked capacitor on a semiconductor wafer, the method comprising the following steps: providing a first node for electrical connection with a capacitor plate; providing a second node; providing an underlying layer of insulating material atop the wafer; providing a combination etch stop and oxidation barrier insulative layer over the underlying insulating layer, the combination layer being different in composition from the insulating material of the underlying layer; providing an intermediate layer of insulating material over the combination layer, the insulating material of the intermediate layer being different in composition from the insulating material of the combination layer with the insulating material of the intermediate layer being selectively etchable relative to the insulating material of the combination layer; etching a capacitor contact opening through the intermediate, combination and underlying insulating layers to the first node; providing a capacitor storage node within the capacitor contact opening in electrical connection with the first node, the storage node having outer sidewall surfaces; etching the intermediate insulating layer selectively relative to the capacitor storage node and combination layer, and using the combination layer as an etch stop during such etching to expose only a portion of the outer surfaces of the capacitor storage node sidewalls; providing a capacitor dielectric layer over the outer sidewall surfaces of the capacitor storage node; providing a cell electrically conductive oxidizable material layer over the capacitor dielectric layer, the cell layer having an outer surface; providing an electrically insulative oxidation barrier layer over the cell layer; providing an overlying layer of insulating material above the oxidation barrier layer; providing a masking layer of the same material as the combination layer above the overlying layer, the masking layer being provided to a thickness which is greater than that of the combination layer; etching a first opening over the second node through the overlying, oxidation barrier and cell layers using the combination layer as an etch stop during such first opening etching, the first opening having sidewalls, the first opening sidewalls including an exposed edge of the cell layer; exposing the wafer having the first opening to an oxidizing ambient to oxidize the cell layer exposed edge, the oxidation barrier layer during such oxidation exposure inhibiting oxidation of the outer surface oft he cell layer, the combination layer during such oxidation exposure inhibiting oxidation of the capacitor storage node; etching the combination layer from within the first opening; etching the underlying layer from within the first opening to outwardly expose the second node for electrical contact; and plugging the first opening with electrically conductive material.

Claim 19

A semiconductor processing method of forming a memory cell of claim 15 wherein the oxidation barrier layer thickness is at least about 150 Angstroms.

Claim 20

A semiconductor processing method of forming a memory cell of claim 15 wherein the oxidation barrier layer thickness is from about 250 Angstroms to about 1500 Angstroms.

Claim 21

A semiconductor processing method of forming a memory cell of claim 15 wherein the combination layer is provided to a thickness of from about 100 Angstroms to about 4000 Angstroms.

Claim 22

A semiconductor processing method of forming a memory cell of claim 15 wherein the overlying and underlying insulating layers constitute the same material.

Claim 23

A semiconductor processing method of forming a memory cell of claim 15 wherein the combination layer comprises nitride.

Claim 24

A semiconductor processing method of forming a memory cell of claim 15 wherein the combination layer comprises SiO 2 deposited by decomposition of tetraethylorthosilicate (TEOS), the underlying layer comprising SiO 2 of another form.

Claim 25

A semiconductor processing method of forming a memory cell of claim 15 wherein the overlying and underlying layers comprise oxide, and the combination layer comprises nitride.