US4965221A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Spacer isolation method for minimizing parasitic sidewall capacitance and creating fully recessed field oxide regions
Assignee: Micron Technology Inc
•
Filing: 1989-03-15
•
Granted: 1990-10-23
•
Expires: 2009-03-15
Abstract
Abstract A modification of the LOCal Oxidation of Silicon (LOCOS) isolation process, whereby prior to the oxidation of silicon substrate that is exposed upon etching the protective CVD nitride layer, a conformal layer of CVD oxide is deposited on the surface of the array. Following an anisotropic etch of the conformal layer, a portion of the conformal layer remains about the peripheries of the etched apertures within the nitride layer. These "spacers" will serve as an anti-encroachment device during field oxide growth and physically offset a subsequent silicon etch. Following a potassium hydroxide etch, which creates sloped-wall trenches in the array regions where silicon substrate is unprotected, the array receives a field implant. The spacers prevent the implanting of the channel-stop impurity near the active areas. Following the implant process, the array is subjected to a wet oxidation process which grows the field oxide regions. Oxide growth is allowed to proceed until the oxide thickness is approximately triple the original depth of the trenches. Following the wet oxidation, the field oxide is etched back with dilute hydrofluoric acid to the point where the upper surface of the field oxide is coplanar with the active areas. This modified LOCOS process provides fully-recessed field oxide regions, dramatically reduces the size of the bird's beak region, and virtually eliminates the problem of channel-stop implant encroachment.
Inventors
- 👤 Charles H. Dennison
- 👤 Fernando Gonzalez
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 12:05
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/10; H10W10/13; H10P; H10P50/00; H10P50/69; H10P50/691; H10P50/693; H10P50/695; H10W10/01; H10W10/011; H10W10/012; H10W10/0121; H10W10/0124; H10W10/0125; H10W10/0126
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
262 words
A spacer isolation method for minimizing parasitic sidewall capacitance and creating fully-recessed field oxide isolation regions within an integrated circuit array fabricated on a silicon substrate, comprising the following steps: (a) growth of a pad oxide layer on the upper surface of the silicon substrate; (b) deposition of a silicon nitride layer on top of the pad oxide layer; (c) deposition of a photoresist mask on top of the silicon nitride layer, thus defining masked and unmasked portions of the silicon nitride layer; (d) etching of the unmasked portions of the nitride layer to expose the pad oxide below; (e) stripping of the photoresist mask; (f) deposition of a conformal spacer-material layer over the surface of the array; (g) anisotropic etching of the spacer-material layer to such an extent that the pad oxide which was exposed prior to the deposition of the spacer-material layer is etched away to expose the silicon substrate below, and a portion of the spacer-material layer remains as spacers about the peripheries of apertures etched within the nitride layer; (h) etching of exposed silicon substrate within the array to form trenches in the silicon substrate; (i) implanting of a field-stop impurity in the silicon substrate directly beneath the trenches; (j) oxidation of the silicon substrate that forms the walls and floor of the trenches to such an extent that silicon oxide has grown to a level that is higher than that of the surrounding silicon nitride-masked silicon substrate; and (k) etching of the silicon oxide to the point where it is essentially coplanar with the surrounding silicon substrate.
Claim 2
Dependent Claim
262 words
A spacer isolation method for minimizing parasitic sidewall capacitance and creating fully-recessed field oxide isolation regions within an integrated circuit array fabricated on a silicon substrate, comprising the following steps: (a) growth of a pad oxide layer on the upper surface of the silicon substrate; (b) deposition of a silicon nitride layer on top of the pad oxide layer; (c) deposition of a photoresist mask on top of the silicon nitride layer, thus defining masked and unmasked portions of the silicon nitride layer; (d) etching of the unmasked portions of the nitride layer to expose the pad oxide below; (e) stripping of the photoresist mask; (f) deposition of a conformal spacer-material layer over the surface of the array; (g) anisotropic etching of the spacer-material layer to such an extent that the pad oxide which was exposed prior to the deposition of the spacer-material layer is etched away to expose the silicon substrate below, and a portion of the spacer-material layer remains as spacers about the peripheries of apertures etched within the nitride layer; (h) etching of exposed silicon substrate within the array to form trenches in the silicon substrate; (i) implanting of a field-stop impurity in the silicon substrate directly beneath the trenches; (j) oxidation of the silicon substrate that forms the walls and floor of the trenches to such an extent that silicon oxide has grown to a level that is higher than that of the surrounding silicon nitride-masked silicon substrate; and (k) etching of the silicon oxide to the point where it is essentially coplanar with the surrounding silicon substrate.
Claim 3
Dependent Claim
29 words
The method of claim 1, wherein said etching of the exposed silicon substrate proceeds to a depth that is approximately 35 percent of the desired final field oxide thickness.
Claim 4
Dependent Claim
36 words
The method of claim 2, wherein said oxidation of the silicon substrate is allowed to proceed until the thickness of the oxide formed is approximately four times as great as the original depth of the trenches.
Claim 5
Dependent Claim
12 words
The method of claim 3, wherein said spacer-material layer is CVD oxide.
Claim 6
Dependent Claim
12 words
The method of claim 4, wherein said spacer-material layer is polycrystalline silicon.
Claim 7
Dependent Claim
18 words
The method of claim 4, wherein the etching of the exposed silicon substrate is accomplished using potassium hydroxide.
Claim 8
Dependent Claim
18 words
The method of claim 5, wherein the etching of the exposed silicon substrate is accomplished using potassium hydroxide.
Claim 9
Dependent Claim
20 words
The method of claim 4, wherein the etching of the exposed silicon substrate is accomplished using an anisotropic silicon etch.
Claim 10
Dependent Claim
20 words
The method of claim 5, wherein the etching of the exposed silicon substrate is accomplished using an anisotropic silicon etch.
Claim 11
Dependent Claim
20 words
The method of claim 4, wherein the etching of the exposed silicon substrate is accomplished using an isotropic silicon etch.
Claim 12
Dependent Claim
20 words
The method of claim 5, wherein the etching of the exposed silicon substrate is accomplished using an isotropic silicon etch.
References Cited (Backward Citations)
US4472240A
Cited
US4435446A
Cited
US4538343A
Cited
JPS6132540A
Cited
USH204H
Cited
JPS61191046A
Cited
JPS61247051A
Cited
JPS6281041A
Cited
JPS62232143A
Cited
US4845048A
Cited
JPS63100743A
Cited
GB2198882A
Cited
JPS63202935A
Cited
US4923563A
Cited
JPS6435929A
Cited
JPH0223934A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-10-22 | 1994-04-23 | 1994-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-10-22 | 1998-04-23 | 1998-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-10-22 | 2002-04-23 | 2002-10-23 | $7700.00 | Window Closed / Lapsed |