Patent US1668812A successfully refreshed from Google Patents.
Patent US5648911A successfully refreshed from Google Patents.
US5648911A
Expired / Lapsed
US
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Method of minimizing area for fanout chains in high-speed networks
Assignee: Hewlett Packard Development Co LP
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Filing: 1996-08-30
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Granted: 1997-07-15
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Expires: 2016-08-30
Abstract
Abstract The method for efficiently providing an optimized fanout network includes the steps of providing a series chain of inverters for driving a number of loads. Each load is assigned to a given location of the inverter chain according to the polarity and the required time of the load. Tree-covering techniques are used in conjunction with dynamic programming to minimize the total area of the fanout chain by selecting and sizing the gates to be used in the fanout chain. With such an arrangement, a minimal area fanout chain which satisfies the timing constraints of each load is provided.
Inventors
- 👤 Joel Joseph Grodstein
- 👤 Kolar L. Kodandapani
- 👤 Herve Touati
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 22:53
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/327
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
93 words
A method for providing a fanout network to drive a plurality of signals in an integrated circuit, each of said signals driving a plurality of loads, said method comprising the steps of: coupling, to each one of said signals, a fixed number of a plurality of series coupled inverters; at each signal, assigning each one said associated plurality of loads be coupled to an output of one of said plurality of inverters; and mapping each of said plurality of inverters to a gate in a library of gates to provide a fanout network.
Claim 2
Independent Claim
93 words
A method for providing a fanout network to drive a plurality of signals in an integrated circuit, each of said signals driving a plurality of loads, said method comprising the steps of: coupling, to each one of said signals, a fixed number of a plurality of series coupled inverters; at each signal, assigning each one said associated plurality of loads be coupled to an output of one of said plurality of inverters; and mapping each of said plurality of inverters to a gate in a library of gates to provide a fanout network.
Claim 3
Dependent Claim
98 words
The method according to claim 1, further comprising the steps of: calculating the area of said fanout network; determining a propagation delay through said fanout network; comparing said area against the area of a stored fanout network; replacing said stored fanout network with said fanout network if said propagation delay of said fanout network is less than or equal to a predetermined delay and if said area of said fanout network is less than the area of said stored fanout network; repeating said steps of assigning, mapping, determining, calculating, comparing and replacing for a predetermined plurality of assignments.
Claim 4
Dependent Claim
45 words
The method according to claim 1, wherein said step of assigning each of said plurality of loads further comprises the steps of: determining the required time for each of said loads; and ordering said plurality of loads in an order of successively increasing required times.
Claim 5
Dependent Claim
47 words
The method according to claim 1, wherein said step of assigning each of said plurality of loads further comprises the steps of: determining the signal polarity of each load; and assigning each of said loads to one of said plurality of coupled inverters providing said signal polarity.
Claim 6
Dependent Claim
114 words
The method according to claim 1, wherein said step of mapping further comprises steps of: determining the input capacitance of the first inverter of said plurality of series coupled inverters; allocating a plurality of alternative gate types for said inverter, each alternative capable of providing a corresponding plurality of output drive; repeating said steps of determining the input capacitance and providing a plurality of alternative gates for each inverter in said plurality of series coupled inverters; evaluating the output drive driven of the last inverter of said plurality of series coupled inverters; and selecting, for each gate, a gate type from said plurality of alternative gates responsive to the output drive of each gate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-07-14 | 2001-01-13 | 2001-07-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-07-14 | 2005-01-13 | 2005-07-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-07-14 | 2009-01-13 | 2009-07-15 | $7700.00 | Window Closed / Lapsed |