Cell based ALU with tree structured carry, inverting logic and balanced loading

Claim 2

An arithmetic logic unit for executing a selected arithmetic operation on first and second digital code signals comprising: a front end portion having a first plurality of input terminals to which respective bit signals of said first digital code signal are applied and a second plurality of input terminals to which respective bit signals of said second digital code signal are applied, said front end portion including arithmetic operation defining control lines and means for generating propagate and generate term signals for the respective bit positions of said digital code signals in accordance with logic signals applied to said arithmetic function defining control lines; a carry propagation portion having a plurality of inputs coupled to receive from said front end portion the propagate and generate term signals for said respective bit positions, said carry propagation portion comprising carry propagation logic circuits and inverter circuits interconnected in a tree structure between said plurality of inputs and a plurality of outputs and providing at said plurality of outputs respective carry propagation signals associated with said respective bit positions; and an output portion, coupled to said carry propagation portion and to said front end portion, and including means for logically combining propagate and generate signals with carry propagation signals to derive an arithmetic operation output code representative of an arithmetic operation executed on said first and second digital code signals.

Claim 3

An arithmetic logic unit according to claim 1, wherein said carry propagation logic circuits are interconnected such that the maximum loading of any carry propagation logic circuit by other carry propagation logic circuits connected thereto is three.

Claim 4

An x-bit arithmetic logic unit cell through which an n-bit arithmetic logic unit for executing a selected arithmetic operation having a tree-structured carry may be configured by interconnecting n repeats of said x-bit cell structure, said cell comprising: first means for receiving x-bit input signals and generating therefrom propagate and generate term signals associated with said x-bits and including arithmetic operation defining control lines and means for generating propagate and generate term signals for the said x-bit input signals in accordance with logic signals applied to said arithmetic function defining control lines; and second means for receiving propagate and generate term signals and a carry signal and producing therefrom x-bit arithmetic operation representative signals, said second means including a carry propagation circuit formed of plurality of interconnected carry tree gate circuits and inverter circuits.

Claim 5

An x-bit arithmetic logic unit cell through which an n-bit arithmetic logic unit for executing a selected arithmetic operation having a tree-structured carry may be configured by interconnecting n repeats of said x-bit cell structure, said cell comprising: first means for receiving x-bit input signals and generating therefrom propagate and generate term signals associated with said x-bits and including arithmetic operation defining control lines and means for generating propagate and generate term signals for the said x-bit input signals in accordance with logic signals applied to said arithmetic function defining control lines; and second means for receiving propagate and generate term signals and a carry signal and producing therefrom x-bit arithmetic operation representative signals, said second means including a carry propagation circuit formed of plurality of interconnected carry tree gate circuits and inverter circuits.

Claim 6

An x-bit arithmetic logic unit cell according to claim 3, wherein said x-bit cell is a two-bit cell and said x-bit input signals for said cell comprise immediately successive bit signals A N and A N-1 and B N and B N-1 ,for first and second digital input signals A and B, respectively, and said first means generates propagate term signal P N-1 and P N and generate term signals G N-1 and G N , and said second means generates propagate term signals P N-1 BAR, and P N'BAR and generate term signals G N-1 BAR, G N' BAR, in the course of generating a further carry signal and said x-bit arithmetic operation representative signals.

Claim 7

An x-bit arithmetic logic unit cell according to claim 4, wherein said second means includes means for providing individual access to said propagate and generate term signals G N-1 BAR, G N 'BAR, and P N 'BAR.

Claim 8

An x-bit arithmetic logic unit cell according to claim 4, wherein said plurality of carry tree gate circuits and inverter circuits are comprised of inverting CMOS logic and are interconnected such that the maximum fanout of any carry tree gate circuit for implementing a 32-bit arithmetic logic unit by other carry tree gate circuits connected thereto is three.

Claim 9

An x-bit arithmetic logic unit cell according to claim 6, wherein said second means comprises a first carry-tree gate providing an AND/NOR function and a second carry-tree gate providing an OR/NAND function, said first carry-tree gate providing an AND/NOR function and a second carry-tree gate providing an OR/NAND function, said first carry-tree gate connected to receive said F N-1 term and P N term at the AND inputs and to receive said G N term at a NOR input, and including means for providing individual access to inputs of said second carry-tree gate.

Claim 10

An x-bit arithmetic logic unit cell according to claim 7, wherein said second means further comprises a first output portion and a second output portion, each output portion comprising an AND/NOR gate having a first AND input connected to receive a carry-in signal and having its output connected to an output gate.

Claim 11

An x-bit arithmetic logic unit cell according to claim 8, wherein said output gate comprises and EXCLUSIVE OR gate.

Claim 12

An x-bit arithmetic logic unit cell according to claim 8, wherein said output gate comprises an EXCLUSIVE NOR gate.

Claim 13

An x-bit arithmetic logic unit cell according to claim 9, wherein said P N term signal is provided to an inverter to generate a P N BAR signal and said P N BAR signal is supplied to said output gate of said second output portion at an EXCLUSIVE OR input.

Claim 14

An x-bit arithmetic logic unit cell according to claim 8, wherein said P N-1 and said P N term signals are coupled to first and second inputs of a first NAND gate in said second means, and including means for providing individual access to the output of said first NAND gate.

Claim 15

An x-bit arithmetic logic unit cell according to claim 12, further comprising a first NOR gate having an output connected to a second input of said AND/NOR gate of said second output portion.

Claim 16

An x-bit arithmetic logic unit cell according to claim 8, further comprising a second AND/NOR gate having first and second AND inputs and a NOR input and having an individually accessible output, said first AND input being individually accessible, and a second NAND gate having a first individually accessible input and having and individually accessible output, and having a second input connected to said second input of said second AND/NOR gate, said connection of said second NAND input and said second input of said second AND/NOR gate being individually accessible.

Claim 17

An x-bit arithmetic logic unit cell according to claim 14, further comprising a second OR input and a NAND input, said second OR input and said NAND input of said second OR/NAND gate being individually accessible, and a first NOR gate having first and second NOR inputs and a NOR output, said NOR output connected to said first AND input of said AND/NOR gate of said second output portion of said second means, said first NOR input being individually accessible and said second NOR input having an individually accessible connection to said first OR input of said second OR/NAND gate.

Claim 18

An x-bit arithmetic logic unit cell according to claim 15, further comprising a second NOR gate having a first and second individually accessible inputs and an individually accessible output.

Claim 19

An x-bit arithmetic logic unit cell according to claim 16, further comprising first, second and third inverters having individually accessible inputs and outputs.

Claim 20

An x-bit arithmetic logic unit cell according to claim 17, further comprising a fourth inverter having an individually accessible input and an individually accessible output.

Claim 21

An x-bit arithmetic logic unit cell according to claim 18, further comprising a fifth inverter having an individually accessible input and an individually accessible output.

Claim 22

An n-bit arithmetic logic unit cell through which an m-bit arithmetic logic unit having a tree-structured carry may be configured by interconnecting m/n repeats of said n-bit cell structure, said cell comprising: first means for receiving n-bit input signals and including arithmetic operation defining control lines for generating propagate and generate term signals associated with said n-bits in accordance with logic signals applied to said arithmetic function defining control lines; and second means for receiving propagate and generate term signals and a carry signal and producing therefrom n-bit arithmetic logic unit signals, said second means including a carry propagation circuit formed of plurality of interconnected carry tree gate circuits and inverter circuits, each of which is individually accessible.

Claim 23

An n-bit arithmetic logic unit cell through which an m-bit arithmetic logic unit having a tree-structured carry may be configured by interconnecting m/n repeats of said n-bit cell structure, said cell comprising: first means for receiving n-bit input signals and including arithmetic operation defining control lines for generating propagate and generate term signals associated with said n-bits in accordance with logic signals applied to said arithmetic function defining control lines; and second means for receiving propagate and generate term signals and a carry signal and producing therefrom n-bit arithmetic logic unit signals, said second means including a carry propagation circuit formed of plurality of interconnected carry tree gate circuits and inverter circuits, each of which is individually accessible.

Claim 24

An n-bit arithmetic logic unit cell according to claim 20, wherein said second means comprises first, second, third and fourth totally individually accessible inverters.

Claim 25

An n-bit arithmetic logic unit cell according to claim 21, wherein said second means comprises a fifth totally individually accessible inverter.

Claim 26

An n-bit arithmetic logic unit cell according to claim 22, wherein said second means comprises a sixth inverter having a G N-1 term signal coupled to its input and having its output individually accessible.

Claim 27

An n-bit arithmetic logic unit cell according to claim 20, said cell is a two-bit cell, and wherein said P and G term signals include P N-1 , P, G N-1 and G N signals, and wherein said G N-1 and P N term signals are provided supplied to respective AND inputs of a first AND/NOR gate and said G N term signal is applied to the NOR input of said first AND/NOR gate, and wherein the output of said first AND/NOR gate is individually accessible, said G N-1 term signal is coupled to the input of a first inverter and the output of said first inverter is individually accessible, said P N-1 term signal is provided to a first input of a first NAND gate and to the input of a second inverter, and said P N term is provided to a second input of said first NAND gate and to the input of a third inverter, the output of said first NAND gate being individually accessible, said totally individually accessible carry-tree gate comprise, a first OR/AND gate, said plurality of totally individually accessible inverters comprises first, second, third and fourth and fifth inverters, further including a totally individually accessible NOR gate, a second AND/NOR gate having first and second AND inputs, a NOR input and an output, said first AND input, said NOR input and said output being individually accessible, a second NAND gate having first and second inputs and an output, said first input and said output being individually accessible and said second input being connected to said second AND input of said second AND/NOR gate at an individually accessible node, a second AND/NOR gate having first and second AND inputs and a NOR input and an output, said first AND input and said NOR input being individually accessible, said second AND input connected to said carry-in line, a first EXCLUSIVE OR gate having first and second inputs and an output, said first input connected to said output of said second AND/NOR gate and said second input connected to the output of said second inverter, said output providing a SUM N-1 term, a third AND/NOR gate having first and second AND inputs and a NOR input and an output, said second AND input connected to said carry line, a second NOR gate having first and second inputs and an output, said first input being individually accessible and said output being connected to said first input of said third AND/NOR gate, a second OR/NAND gate having first and second OR inputs and a NAND input and an output, said second OR input and said NAND input being individually accessible and said first OR input being connected to said second NOR input of said second NOR gate at an individually accessible node, said output of said second OR/NAND gate connected to said NOR input of said third AND/NOR gate and a second EXCLUSIVE OR gate having first and second inputs and an output, said first input connected to said output of said third AND/NOR gate said second input connected to said output of said third inverter and said output providing a SUM N term signal.

Claim 28

An arithmetic logic unit for executing a selected arithmetic operation on first and second digital code signals comprising: a plurality of arithmetic logic unit cells each of which contains circuitry for implementing one bit of said arithmetic logic unit and includes a front end portion, a carry propagation portion and an output portion, said arithmetic logic unit cells being interconnected so that their front end portions are coupled to receive respective bit signals of said first digital code signal and respective bit signals of said second digital code signal, said front end portions including arithmetic operation defining control lines and means for generating propagate and generate term signals for the respective bit positions of said digital code signals in accordance with logic signals applied to said arithmetic function defining control lines; said carry propagation portions having a plurality of inputs coupled to receive from said front end portion the propagate and generated term signals for said respective bit positions, and comprising carry propagation logic circuits and inverter circuits interconnected in a tree structure between said plurality of inputs and a plurality of outputs and providing at said plurality of outputs respective carry propagation signals associated with said respective bit positions; and said output portions being coupled to said carry propagation portions and to said front end portions, and including means for logically combining propagate and generate signals with carry propagation signals to derive and arithmetic operation representative output code representative of an arithmetic operation on said first and second digital code signals.

Claim 29

An arithmetic logic unit for executing a selected arithmetic operation on first and second digital code signals comprising: a plurality of arithmetic logic unit cells each of which contains circuitry for implementing one bit of said arithmetic logic unit and includes a front end portion, a carry propagation portion and an output portion, said arithmetic logic unit cells being interconnected so that their front end portions are coupled to receive respective bit signals of said first digital code signal and respective bit signals of said second digital code signal, said front end portions including arithmetic operation defining control lines and means for generating propagate and generate term signals for the respective bit positions of said digital code signals in accordance with logic signals applied to said arithmetic function defining control lines; said carry propagation portions having a plurality of inputs coupled to receive from said front end portion the propagate and generated term signals for said respective bit positions, and comprising carry propagation logic circuits and inverter circuits interconnected in a tree structure between said plurality of inputs and a plurality of outputs and providing at said plurality of outputs respective carry propagation signals associated with said respective bit positions; and said output portions being coupled to said carry propagation portions and to said front end portions, and including means for logically combining propagate and generate signals with carry propagation signals to derive and arithmetic operation representative output code representative of an arithmetic operation on said first and second digital code signals.

Claim 30

An arithmetic logic unit according to claim 25, wherein said output portion comprises an AND/NOR gate driving an EXCLUSIVE OR gate.

Claim 31

An arithmetic logic unit according to claim 25, wherein said output portion comprises an AND/NOR gate driving an EXCLUSIVE NOR gate.

Claim 32

An arithmetic logic unit according to claim 27, a generated propagate signal from said propagate and generate portion is coupled to one input of said EXCLUSIVE NOR gate.

Claim 33

An arithmetic logic unit according to claim 25, wherein said carry propagation logic circuits are interconnected such that the maximum loading of any carry propagation logic circuit by other carry propagation logic circuits connected thereto is three.

Claim 34

An arithmetic logic unit according to claim 25, wherein said arithmetic logic unit comprises a 32 bit arithmetic logic unit in which output portions for bits 0-15 are coupled to receive carry propagation signals from said carry propagation portions and a carry-in signal and output portions for bits 16-31 are coupled to receive carry propagation signals from said carry propagation portions and a carry signal from bit 15.