Clock distribution system for an integrated circuit device

Claim 2

A clock signal distribution system for a chip comprising: means for generating a synchronization signal and a plurality of clock signals having respective frequencies that are in an integral fraction relationship to one another and are synchronized at a location, designated the initial location, on the chip; first distributing means for distributing at least one of said plurality of clock signals to each of a plurality of M locations, designated remote locations, on the chip with delay times among said remote locations being approximately equal to one another to a first level of precision; second distributing means for distributing said synchronization signal to each of said remote locations with delay times being approximately equal to one another to a second level of precision greater than said first level of precision; and a plurality of M synchronization means, each located at a respective remote location and responsive to said at least one of said plurality of clock signals at the respective remote location and to said synchronization signal at the respective remote location, for synchronizing said at least one of said plurality of clock signals at the respective remote location; whereby said pluralities of clock signals at said remote locations are characterized by delay times that are approximately equal to each other to said second level of precision notwithstanding the fact that said distributing first means distributes said plurality of clock signals to said remote locations with said first level of precision.

Claim 3

A clock signal distribution system for a chip comprising: means for generating an initial plurality of clock signals having respective frequencies that are in an integral fraction relationship to one another; first synchronization means, responsive to said initial plurality of clock signals, for generating a synchronization signal and for synchronizing said initial plurality of clock signals at a location, designated the initial location, on the chip; first distributing means for distributing at least one of said initial plurality of clock signals to each of a plurality of M locations, designated remote locations, on the chip with delay times among said remote locations being approximately equal to one another to a first level of precision; second distributing means for distributing said synchronization signal to each of said remote locations with delay times being approximately equal to one another to a second level of precision greater than said first level of precision; and a plurality of M second synchronization means, each located at a respective remote location and responsive to said at least one of said initial plurality of clock signals at the respective remote location and to the synchronization signal at the respective remote location, for resynchronizing said at least one of said initial plurality of clock signals at the respective remote location, to form pluralities of resynchronized clock signals; whereby said pluralities of resynchronized clock signals at said remote locations are characterized by delay times that are approximately equal to each other to said second level of precision notwithstanding the fact that said first distributing means distributes said plurality of clock signals to said remote locations with said first level of precision.

Claim 4

A clock signal distribution system for a chip comprising: means for generating an initial plurality of clock signals having respective frequencies that are in an integral fraction relationship to one another; first synchronization means, responsive to said initial plurality of clock signals, for generating a synchronization signal and for synchronizing said initial plurality of clock signals at a location, designated the initial location, on the chip; first distributing means for distributing at least one of said initial plurality of clock signals to each of a plurality of M locations, designated remote locations, on the chip with delay times among said remote locations being approximately equal to one another to a first level of precision; second distributing means for distributing said synchronization signal to each of said remote locations with delay times being approximately equal to one another to a second level of precision greater than said first level of precision; and a plurality of M second synchronization means, each located at a respective remote location and responsive to said at least one of said initial plurality of clock signals at the respective remote location and to the synchronization signal at the respective remote location, for resynchronizing said at least one of said initial plurality of clock signals at the respective remote location, to form pluralities of resynchronized clock signals; whereby said pluralities of resynchronized clock signals at said remote locations are characterized by delay times that are approximately equal to each other to said second level of precision notwithstanding the fact that said first distributing means distributes said plurality of clock signals to said remote locations with said first level of precision.

Claim 5

A clock signal distribution system for a chip comprising: means for generating an initial plurality of clock signals having respective frequencies that are in an integral fraction relationship to one another, each of said initial plurality of clock signals having at least one timing mark during each cycle; first synchronization means, responsive to said initial plurality of clock signals, for generating a synchronization signal and a first plurality of derived clock signals at a location, designated the initial location, on the chip; said first plurality of derived clock signals having the same frequencies and timing marks as said initial plurality of clock signals and further being characterized in that said first plurality of derived clock signals have respective timing marks that occur at substantially the same time at repeating intervals defined by said integral fraction relationship; first distributing means for distributing at least one of said first plurality of derived clock signals to each of a plurality of M locations, designated remote locations, on the chip; said first distributing means being characterized by delay times for said at least one of said first plurality of derived clock signals at each of said remote locations, said delay times being approximately equal to one another to a first level of precision; second distributing means for distributing said synchronization signal to each of said remote locations; said second distributing means being characterized by delay times for said synchronization signal at each of said remote locations, said delay times being approximately equal to one another to a second level of precision greater than said first level of precision; a plurality of M second synchronization means, each located at a respective remote location and responsive to the first plurality of derived clock signals at the respective remote location and to the synchronization signal at the respective remote location, for generating a second plurality of derived clock signals at the respective remote location; for each given remote location, the second plurality of derived clock signals at the given remote location having the same frequencies and timing marks as said initial plurality of clock signals and further being characterized in that the second plurality of derived clock signals at the given remote location have respective timing marks that occur periodically with a period defined by said integral fraction relationship; whereby the second plurality of derived clock signals at said remote locations are characterized by delay times that are approximately equal to each other to said second level of precision notwithstanding the fact that said first distributing means distributes said first plurality of derived clock signals at said remote locations with said first level of precision.

Claim 6

A clock signal distribution system for a chip comprising: means for generating an initial plurality of clock signals having respective frequencies that are in an integral fraction relationship to one another, each of said initial plurality of clock signals having at least one timing mark during each cycle; first synchronization means, responsive to said initial plurality of clock signals, for generating a synchronization signal and a first plurality of derived clock signals at a location, designated the initial location, on the chip; said first plurality of derived clock signals having the same frequencies and timing marks as said initial plurality of clock signals and further being characterized in that said first plurality of derived clock signals have respective timing marks that occur at substantially the same time at repeating intervals defined by said integral fraction relationship; first distributing means for distributing at least one of said first plurality of derived clock signals to each of a plurality of M locations, designated remote locations, on the chip; said first distributing means being characterized by delay times for said at least one of said first plurality of derived clock signals at each of said remote locations, said delay times being approximately equal to one another to a first level of precision; second distributing means for distributing said synchronization signal to each of said remote locations; said second distributing means being characterized by delay times for said synchronization signal at each of said remote locations, said delay times being approximately equal to one another to a second level of precision greater than said first level of precision; a plurality of M second synchronization means, each located at a respective remote location and responsive to the first plurality of derived clock signals at the respective remote location and to the synchronization signal at the respective remote location, for generating a second plurality of derived clock signals at the respective remote location; for each given remote location, the second plurality of derived clock signals at the given remote location having the same frequencies and timing marks as said initial plurality of clock signals and further being characterized in that the second plurality of derived clock signals at the given remote location have respective timing marks that occur periodically with a period defined by said integral fraction relationship; whereby the second plurality of derived clock signals at said remote locations are characterized by delay times that are approximately equal to each other to said second level of precision notwithstanding the fact that said first distributing means distributes said first plurality of derived clock signals at said remote locations with said first level of precision.

Claim 7

The clock signal distribution system for a chip of claim 3, wherein said timing mark of a clock signal is one of a rising edge or a falling edge.

Claim 8

A clock generator comprising: means for generating a plurality of clock signals having respective frequencies that are in an integral fraction relationship to one another; each given clock signal of said plurality of clock signals having at least one timing mark during each cycle of said given clock signal; said plurality of clock signals having respective timing marks that occur periodically with a period defined by said integral fraction relationship; said plurality of clock signals having first and second subsets of clock signals characterized by first and second subsets of frequencies wherein each frequency in said first subset is a particular integer multiple of one frequency in said second subset, said particular integer being designated the cycle-down divisor; means, responsive to said first and second subsets of clock signals and to an input signal specifying which of said first and second subsets of clock signals is to be selected, for generating a select signal, including means for preventing said select signal from changing state except during an interval when the clock signals in said first and second subsets have relative phases equal to a predefined phase relationship; and means, responsive to said select signal, for selecting one or the other of said first and second subsets of clock signals for output.

Claim 9

A clock generator comprising: means for generating a plurality of clock signals having respective frequencies that are in an integral fraction relationship to one another; each given clock signal of said plurality of clock signals having at least one timing mark during each cycle of said given clock signal; said plurality of clock signals having respective timing marks that occur periodically with a period defined by said integral fraction relationship; said plurality of clock signals having first and second subsets of clock signals characterized by first and second subsets of frequencies wherein each frequency in said first subset is a particular integer multiple of one frequency in said second subset, said particular integer being designated the cycle-down divisor; means, responsive to said first and second subsets of clock signals and to an input signal specifying which of said first and second subsets of clock signals is to be selected, for generating a select signal, including means for preventing said select signal from changing state except during an interval when the clock signals in said first and second subsets have relative phases equal to a predefined phase relationship; and means, responsive to said select signal, for selecting one or the other of said first and second subsets of clock signals for output.

Claim 10

The clock generator of claim 5 wherein said first and second subsets of frequencies include at least one frequency in common.

Claim 11

The clock generator of claim 5 wherein said predefined phase relationship is that all the clock signals in said first and second subsets have their respective leading edges aligned.

Claim 12

The clock generator of claim 5, wherein said timing mark is one of a rising edge or a falling edge.

Claim 13

A clock signal distribution system for a chip comprising: a synchronization circuit which outputs a synchronization signal and a plurality of clock signals having respective frequencies that are in an integral fraction relationship to one another and are synchronized at a location, designated the initial location, on the chip; a set of clock distribution lines which distribute at least one of said plurality of clock signals to each of a plurality of M locations on the chip, designated remote locations, with delay times among said remote locations being approximately equal to one another to a first level of precision; a set of synchronization distribution lines which distribute said synchronization signal to each of said remote locations with delay times being approximately equal to one another to a second level of precision greater than said first level of precision; and a plurality of M remote clock synchronization circuits, each located at a respective remote location and responsive to said at least one of said plurality of clock signals at the respective remote location and to said synchronization signal at the respective remote location, wherein a remote clock synchronization circuit synchronizes said at least one of said plurality of clock signals at said respective remote location; whereby said pluralities of clock signals at said remote locations are characterized by delay times that are approximately equal to each other to said second level of precision notwithstanding the fact that said set of clock distribution lines distribute said plurality of clock signals to said remote locations with said first level of precision.

Claim 14

A clock signal distribution system for a chip comprising: a synchronization circuit which outputs a synchronization signal and a plurality of clock signals having respective frequencies that are in an integral fraction relationship to one another and are synchronized at a location, designated the initial location, on the chip; a set of clock distribution lines which distribute at least one of said plurality of clock signals to each of a plurality of M locations on the chip, designated remote locations, with delay times among said remote locations being approximately equal to one another to a first level of precision; a set of synchronization distribution lines which distribute said synchronization signal to each of said remote locations with delay times being approximately equal to one another to a second level of precision greater than said first level of precision; and a plurality of M remote clock synchronization circuits, each located at a respective remote location and responsive to said at least one of said plurality of clock signals at the respective remote location and to said synchronization signal at the respective remote location, wherein a remote clock synchronization circuit synchronizes said at least one of said plurality of clock signals at said respective remote location; whereby said pluralities of clock signals at said remote locations are characterized by delay times that are approximately equal to each other to said second level of precision notwithstanding the fact that said set of clock distribution lines distribute said plurality of clock signals to said remote locations with said first level of precision.

Claim 15

A clock generator comprising: a clock generator circuit which outputs a plurality of clock signals having respective frequencies that are in an integral fraction relationship to one another; each given clock signal of said plurality of clock signals having at least one timing mark during each cycle of said given clock signal; said plurality of clock signals having respective timing marks that occur periodically with a period defined by said integral fraction relationship; said plurality of clock signals having first and second subsets of clock signals characterized by first and second subsets of frequencies wherein each frequency in said first subset is a particular integer multiple of one frequency in said second subset, said particular integer being designated the cycle-down divisor; a clock-divider responsive to said first and second subsets of clock signals and to an input signal specifying which of said first and second subsets of clock signals is to be selected, which generates a select signal, wherein said select signal does not change state except during an interval when the clock signals in said first and second subsets have relative phases equal to a predefined phase relationship; and a multiplexer with a select input coupled to receive said select signal and inputs for said first and second subsets of clock signals, and an output which outputs said first subset of clock signals when said select signal is in a first state and said second subset of clock signals when said select signal is in a second state.

Claim 16

A clock generator comprising: a clock generator circuit which outputs a plurality of clock signals having respective frequencies that are in an integral fraction relationship to one another; each given clock signal of said plurality of clock signals having at least one timing mark during each cycle of said given clock signal; said plurality of clock signals having respective timing marks that occur periodically with a period defined by said integral fraction relationship; said plurality of clock signals having first and second subsets of clock signals characterized by first and second subsets of frequencies wherein each frequency in said first subset is a particular integer multiple of one frequency in said second subset, said particular integer being designated the cycle-down divisor; a clock-divider responsive to said first and second subsets of clock signals and to an input signal specifying which of said first and second subsets of clock signals is to be selected, which generates a select signal, wherein said select signal does not change state except during an interval when the clock signals in said first and second subsets have relative phases equal to a predefined phase relationship; and a multiplexer with a select input coupled to receive said select signal and inputs for said first and second subsets of clock signals, and an output which outputs said first subset of clock signals when said select signal is in a first state and said second subset of clock signals when said select signal is in a second state.