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US5646550A
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High reliability output buffer for multiple voltage system
Assignee: NXP USA Inc
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Filing: 1996-02-22
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Granted: 1997-07-08
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Expires: 2016-02-22
Abstract
Abstract An output buffer (30) is connected to an output signal line and receives an internal power supply voltage, for example 3.3 volts, which is lower than a voltage, for example 5 volts, that other devices which may be connected to the output signal line are able to drive. To protect an output transistor (71) from the harmful effects of the higher voltages on the output signal line, the output buffer (30) includes a special bulk biasing circuit (80). The bulk biasing circuit (80) biases the bulk of the output transistor (71) at an internal power supply voltage when the output buffer is driving and when not driving to a voltage determined by the output signal. To prevent overlap currents, the output buffer (30) includes a special gate biasing circuit (100), which momentarily drives the gate of the output transistor (71) to a voltage equal to the internal power supply voltage when the output buffer (30) stops driving.
Inventors
- 👤 Jules D. Campbell, Jr.
- 👤 Rene M. Delgado
- 👤 Steve Lim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 13:25
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/09425; H03K19/09429; H03K19/0008; H03K19/0013
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
347 words
A high reliability output buffer for a multiple voltage system comprising: an enable input terminal for receiving an enable signal; a predriver circuit having a data input terminal for receiving a data signal, a control input terminal coupled to said enable input terminal, and first and second output terminals for providing first and second predrive signals; said predriver circuit providing first predrive at a logic state corresponding to said data signal when said enable signal is active, and providing said first predrive signal at a logic state corresponding to a first power supply voltage terminal when said enable signal is inactive; said predriver circuit providing said second predrive signal at a logic state corresponding to said data signal when said enable signal is active, and providing said second predrive signal at a logic state corresponding to a second power supply voltage terminal when said enable signal is inactive; a first transistor of a first conductivity type having a first current electrode coupled to said first power supply voltage terminal, a control electrode coupled to the first output terminal of said predriver circuit, a second current electrode for providing an output signal, and a bulk electrode; a second transistor of a second conductivity type having a first current electrode coupled to said second current electrode of said first transistor, a control electrode for receiving said second predrive signal, and a second current electrode coupled to said second power supply voltage terminal; and a bulk biasing circuit having an input terminal coupled to said enable input terminal, and an output terminal coupled to said bulk of said first transistor, said bulk biasing circuit coupling said bulk electrode of said first transistor to said first power supply voltage terminal in response to said enable signal, wherein said bulk biasing circuit further has a second input terminal for receiving said output signal, and wherein said bulk biasing circuit further couples said bulk of said first transistor to said output signal when a voltage of said output signal exceeds a voltage of said first power supply voltage terminal by a predetermined amount.
Claim 2
Dependent Claim
347 words
A high reliability output buffer for a multiple voltage system comprising: an enable input terminal for receiving an enable signal; a predriver circuit having a data input terminal for receiving a data signal, a control input terminal coupled to said enable input terminal, and first and second output terminals for providing first and second predrive signals; said predriver circuit providing first predrive at a logic state corresponding to said data signal when said enable signal is active, and providing said first predrive signal at a logic state corresponding to a first power supply voltage terminal when said enable signal is inactive; said predriver circuit providing said second predrive signal at a logic state corresponding to said data signal when said enable signal is active, and providing said second predrive signal at a logic state corresponding to a second power supply voltage terminal when said enable signal is inactive; a first transistor of a first conductivity type having a first current electrode coupled to said first power supply voltage terminal, a control electrode coupled to the first output terminal of said predriver circuit, a second current electrode for providing an output signal, and a bulk electrode; a second transistor of a second conductivity type having a first current electrode coupled to said second current electrode of said first transistor, a control electrode for receiving said second predrive signal, and a second current electrode coupled to said second power supply voltage terminal; and a bulk biasing circuit having an input terminal coupled to said enable input terminal, and an output terminal coupled to said bulk of said first transistor, said bulk biasing circuit coupling said bulk electrode of said first transistor to said first power supply voltage terminal in response to said enable signal, wherein said bulk biasing circuit further has a second input terminal for receiving said output signal, and wherein said bulk biasing circuit further couples said bulk of said first transistor to said output signal when a voltage of said output signal exceeds a voltage of said first power supply voltage terminal by a predetermined amount.
Claim 3
Dependent Claim
112 words
The output buffer of claim 1 wherein said bulk biasing circuit comprises: a third transistor having a first current electrode coupled to said first power supply voltage terminal, a control electrode for receiving said output signal, a second current electrode coupled to said bulk electrode of said first transistor, and a bulk electrode coupled to said second current electrode thereof; and a fourth transistor having a first current electrode for receiving said output signal, a control electrode coupled to said first power supply voltage terminal, a second current electrode coupled to said bulk electrode of said first transistor, and a bulk electrode coupled to said second current electrode of said third transistor.
Claim 4
Dependent Claim
125 words
The output buffer of claim 2 wherein said bulk biasing circuit further comprises: a fifth transistor having a first current electrode coupled to said first power supply voltage terminal, a control electrode coupled to said second current electrode of said first transistor, a second current electrode coupled to said second current electrode of said first transistor, and a bulk electrode coupled to said second current electrode of said first transistor; and a sixth transistor having a first current electrode for receiving said output signal, a control electrode coupled to said second current electrode of said first transistor, a second current electrode coupled to said second current electrode of said first transistor, and a bulk electrode coupled to said second current electrode of said first transistor.
Claim 5
Dependent Claim
67 words
The output buffer of claim 1 further comprising a gate biasing circuit having an input terminal coupled to said enable input terminal, and an output terminal coupled to said control electrode of said first transistor, said gate biasing circuit coupling said control electrode of said first transistor to said first power supply voltage terminal for a predetermined time in response to an inactivation of said enable signal.
Claim 6
Dependent Claim
87 words
The output buffer of claim 4 wherein said gate biasing circuit comprises: a one-shot having an input terminal coupled to said enable input terminal, and an output terminal for providing a shutoff pulse for said predetermined time; and logic means coupled to said output terminal of said one-shot and to said control electrode of said first transistor, for providing a voltage to said control electrode of said first transistor substantially equal to a voltage at said first power supply voltage terminal in response to said shutoff pulse.
Claim 7
Dependent Claim
296 words
A high reliability output buffer for a multiple voltage system comprising: an enable input terminal for receiving an enable signal; a predriver circuit having a data input terminal for receiving a data signal, a control input terminal coupled to said enable input terminal, and first and second output terminals for providing first and second predrive signals; said predriver circuit providing first predrive at a logic state corresponding to said data signal when said enable signal is active, and providing said first predrive signal at a logic state corresponding to a first power supply voltage terminal when said enable signal is inactive; said predriver circuit providing said second predrive signal at a logic state corresponding to said data signal when said enable signal is active, and providing said second predrive signal at a logic state corresponding to a second power supply voltage terminal when said enable signal is inactive; a first transistor of a first conductivity type having a first current electrode coupled to said first power supply voltage terminal, a control electrode for receiving said first predrive signal, a second current electrode for providing an output signal, and a bulk electrode; a second transistor of a second conductivity type having a first current electrode coupled to said second current electrode of said first transistor, a control electrode for receiving said second predrive signal, and a second current electrode coupled to said second power supply voltage terminal; and a gate biasing circuit having an input terminal coupled to said enable input terminal, and an output terminal coupled to said control electrode of said first transistor, said gate biasing circuit coupling said control electrode of said first transistor to said first power supply voltage terminal for a predetermined time in response to an inactivation of said enable signal.
Claim 8
Dependent Claim
296 words
A high reliability output buffer for a multiple voltage system comprising: an enable input terminal for receiving an enable signal; a predriver circuit having a data input terminal for receiving a data signal, a control input terminal coupled to said enable input terminal, and first and second output terminals for providing first and second predrive signals; said predriver circuit providing first predrive at a logic state corresponding to said data signal when said enable signal is active, and providing said first predrive signal at a logic state corresponding to a first power supply voltage terminal when said enable signal is inactive; said predriver circuit providing said second predrive signal at a logic state corresponding to said data signal when said enable signal is active, and providing said second predrive signal at a logic state corresponding to a second power supply voltage terminal when said enable signal is inactive; a first transistor of a first conductivity type having a first current electrode coupled to said first power supply voltage terminal, a control electrode for receiving said first predrive signal, a second current electrode for providing an output signal, and a bulk electrode; a second transistor of a second conductivity type having a first current electrode coupled to said second current electrode of said first transistor, a control electrode for receiving said second predrive signal, and a second current electrode coupled to said second power supply voltage terminal; and a gate biasing circuit having an input terminal coupled to said enable input terminal, and an output terminal coupled to said control electrode of said first transistor, said gate biasing circuit coupling said control electrode of said first transistor to said first power supply voltage terminal for a predetermined time in response to an inactivation of said enable signal.
Claim 9
Dependent Claim
87 words
The output buffer of claim 6 wherein said gate biasing circuit comprises: a one-shot having an input terminal coupled to said enable input terminal, and an output terminal for providing a shutoff pulse for said predetermined time; and logic means coupled to said output terminal of said one-shot and to said control electrode of said first transistor, for providing a voltage to said control electrode of said first transistor substantially equal to a voltage at said first power supply voltage terminal in response to said shutoff pulse.
Claim 10
Dependent Claim
49 words
The output buffer of claim 6 further comprising: a third transistor having a first current electrode coupled to said first output terminal of said predriver circuit, a control electrode coupled to said first power supply voltage terminal, and a second current coupled to said control of said first transistor.
Claim 11
Dependent Claim
28 words
The output buffer of claim 6 wherein said logic circuit comprises nonoverlapping circuit means for making said first and second predrive signals nonoverlapping with respect to each other.
Claim 12
Dependent Claim
70 words
The output buffer of claim 6 wherein said first current electrode of said second transistor is coupled to said second current electrode of said first transistor through a third transistor having a first current electrode coupled to said second current electrode of said first transistor, a gate coupled to said first power supply voltage terminal, and a second current electrode coupled to said first current electrode of said second transistor.
References Cited (Backward Citations)
US4954729A
Cited
US5160855A
Cited
US5266849A
Cited
US5338978A
Cited
US5396128A
Cited
US5467031A
Cited
US5565794A
Cited
US5543733A
Cited
US5546019A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-07-07 | 2001-01-06 | 2001-07-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-07-07 | 2005-01-06 | 2005-07-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-07-07 | 2009-01-06 | 2009-07-08 | $7700.00 | Window Closed / Lapsed |