CMOS I/O circuit with 3.3 volt output and tolerance of 5 volt input

Claim 2

An output buffer circuit, comprising: a first voltage supply node having a first voltage level; a reference voltage supply node having a reference voltage level; an output node having an output voltage level; a logic control circuit having a tristate control input, a logic control input, a first output, a second output, and a third output; a first P channel metal oxide semiconductor field effect transistor having a source, a drain, and a gate wherein said gate of said first P channel metal oxide semiconductor field effect transistor is connected to said first output of said logic control circuit and said source of said first P channel metal oxide semiconductor field effect transistor is connected to said first voltage supply node; a first N channel metal oxide semiconductor field effect transistor having a source, a drain, and a gate wherein said gate of said first N channel metal oxide semiconductor field effect transistor is connected to said second output of said logic control circuit, said source of said first N channel metal oxide semiconductor field effect transistor is connected to said reference voltage supply node and said drain of said first N channel metal oxide semiconductor field effect transistor is connected to said output node; means for preventing leakage current connected between said drain of said first P channel metal oxide semiconductor field effect transistor and said drain of said first N channel metal oxide semiconductor field effect transistor whereby leakage current flowing from said output node through said first P channel metal oxide semiconductor field effect transistor to said first voltage supply node is prevented; and means for output voltage pull up wherein the voltage at said output node is pulled up to said first voltage level when said first P channel metal oxide semiconductor field effect transistor is turned on.

Claim 3

The output buffer circuit of claim 1 wherein said means for preventing leakage current comprises a second N channel metal oxide semiconductor field effect transistor having a source, a drain, and a gate wherein said gate of said second N channel metal oxide semiconductor field effect transistor is connected to said third output of said logic control circuit, said drain of said second N channel metal oxide semiconductor field effect transistor is connected to said drain of said first P channel metal oxide semiconductor field effect transistor, and said source of said second N channel metal oxide semiconductor field effect transistor is connected to said drain of said first N channel metal oxide semiconductor field effect transistor.

Claim 4

The output buffer circuit of claim 1 wherein said means for voltage pull up comprises: an AND INVERT circuit having a first input, a second input, and an output wherein said first input of said AND INVERT circuit is connected to said output node and said second input of said AND INVERT circuit is connected to said third input of said control logic circuit; a second P channel metal oxide semiconductor field effect transistor having a source, a gate, a drain, and an isolation well wherein said gate of said second P channel metal oxide semiconductor field effect transistor is connected to said output of said AND INVERT circuit and said drain of said second P channel metal oxide semiconductor field effect transistor is connected to said output node; a third P channel metal oxide semiconductor field effect transistor having a source, a gate, a drain, and an isolation well wherein said drain of said third P channel metal oxide semiconductor metal oxide semiconductor field effect transistor is connected to said source of said second P channel metal oxide semiconductor field effect transistor and said source of said third metal oxide semiconductor field effect transistor is connected to said first voltage supply node; a fourth P channel metal oxide semiconductor field effect transistor having a source, a gate, a drain, and an isolation well wherein said source of said fourth metal oxide semiconductor field effect transistor is connected to said first voltage supply node, said drain of said fourth P channel metal oxide semiconductor field effect transistor is connected to said isolation well of said second P channel metal oxide semiconductor field effect transistor, and said isolation well of said fourth P channel metal oxide semiconductor field effect transistor is connected to said drain of said third P channel metal oxide semiconductor field effect transistor; a fifth P channel metal oxide semiconductor field effect transistor having a source, a drain, a gate, and an isolation well wherein said drain of said fifth P channel metal oxide semiconductor field effect transistor is connected to said gate of said third P channel metal oxide semiconductor field effect transistor and the gate of said fourth P channel metal oxide semiconductor field effect transistor, said gate of said fifth P channel metal oxide semiconductor field effect transistor is connected to said third output of said logic control circuit, and said source and said isolation well of said fifth P channel metal oxide semiconductor field effect transistor are connected to said output node; and a third N channel metal oxide semiconductor field effect transistor having a source, a drain, a gate, and an isolation well wherein said drain of said third N channel metal oxide semiconductor field effect transistor is connected to said gate of said third P channel metal oxide semiconductor field effect transistor and the gate of said fourth P channel metal oxide semiconductor field effect transistor, said gate of said third N channel metal oxide semiconductor field effect transistor is connected to said third output of said logic control circuit, and said source and said isolation well of said third N channel metal oxide semiconductor field effect transistor are connected to said reference voltage node.

Claim 5

The output buffer circuit of claim 1 wherein said first voltage level is about 3.3 volts.

Claim 6

The output buffer circuit of claim 1 wherein said output voltage level is between about 0 and 5.0 volts.

Claim 7

The output buffer circuit of claim 1 wherein said reference voltage level is about zero volts.

Claim 8

The output buffer circuit of claim 1 wherein the signal at said third output of said control logic circuit is the inverse of the signal at said tristate control input of said control logic circuit.

Claim 9

The output buffer circuit of claim 1 wherein the signal at said first output of said control logic circuit is a logical one level when the signal at the logic control input of the logic control circuit is a logical zero level or the signal at the tristate control input is a logical one level and a logical zero level when the signal at the logic control input of the logic control circuit is a logical one level and the signal at the tristate control input is a logical zero level.

Claim 10

The output buffer circuit of claim 1 wherein the signal at said second output of said control logic circuit is a logical one level when the signal at the logic control input of the logic control circuit is a logical zero level and the signal at the tristate control input is a logical zero level and a logical zero level when the signal at the logic control input of the logic control circuit is a logical one level or the signal at the tristate control input is a logical one level.

Claim 11

The output buffer circuit of claim 1 wherein said control logic circuit further comprises: a sixth P channel metal oxide semiconductor field effect transistor having a gate, a source, and a drain wherein said gate of said sixth P channel metal oxide semiconductor field effect transistor is connected to said logic control input of said control logic circuit, said source of said sixth P channel metal oxide semiconductor field effect transistor is connected to said first voltage supply node, and said drain of said sixth P channel metal oxide semiconductor field effect transistor is connected to said first output of said control logic circuit; a seventh P channel metal oxide semiconductor field effect transistor having a gate, a source, and a drain wherein said gate of said seventh P channel metal oxide semiconductor field effect transistor is connected to said third output of said control logic circuit, said source of said seventh P channel metal oxide semiconductor field effect transistor is connected to said first voltage supply node, and said drain of said seventh P channel metal oxide semiconductor field effect transistor is connected to said first output of said control logic circuit; an eighth P channel metal oxide semiconductor field effect transistor having a gate, a source, and a drain wherein said gate of said eighth P channel metal oxide semiconductor field effect transistor is connected to said tristate control input of said control logic circuit, said source of said eighth P channel metal oxide semiconductor field effect transistor is connected to said first output of said control logic circuit, and said drain of said eighth P channel metal oxide semiconductor field effect transistor is connected to said second output of said control logic circuit; a fourth N channel metal oxide semiconductor field effect transistor having a gate, a source, and a drain wherein said gate of said fourth N channel metal oxide semiconductor field effect transistor is connected to said third output of said control logic circuit, said drain of said fourth N channel metal oxide semiconductor field effect transistor is connected to said first output of said control logic circuit, and said source of said fourth N channel metal oxide semiconductor field effect transistor is connected to said second output of said control logic circuit; a fifth N channel metal oxide semiconductor field effect transistor having a gate, a source, and a drain wherein said gate of said fifth N channel metal oxide semiconductor field effect transistor is connected to said logic control input of said control logic circuit, said drain of said fifth N channel metal oxide semiconductor field effect transistor is connected to said second output of said control logic circuit, and said source of said fifth N channel metal oxide semiconductor field effect transistor is connected to said reference voltage node; a sixth N channel metal oxide semiconductor field effect transistor having a gate, a source, and a drain wherein said gate of said sixth N channel metal oxide semiconductor field effect transistor is connected to said tristate control input of said control logic circuit, said drain of said sixth N channel metal oxide semiconductor field effect transistor is connected to said second output of said control logic circuit, and said source of said sixth N channel metal oxide semiconductor field effect transistor is connected to said reference voltage node; and an inverter having an input and an output wherein said input of said inverter is connected to said tristate control input of said control logic circuit and said output of said inverter is connected to said third output of said control logic circuit.

Claim 12

a voltage pull up circuit, comprising: a first voltage supply node having a first voltage level; an output node having an output voltage level; a reference voltage supply node having a reference voltage level; a control input node; means to pull up the voltage at said output node to said first voltage level when the signal at said control input node is a logical one and the voltage at said output node is above a critical voltage.

Claim 13

a voltage pull up circuit, comprising: a first voltage supply node having a first voltage level; an output node having an output voltage level; a reference voltage supply node having a reference voltage level; a control input node; means to pull up the voltage at said output node to said first voltage level when the signal at said control input node is a logical one and the voltage at said output node is above a critical voltage.

Claim 14

The voltage pull up circuit of claim 11 wherein said means to pull up the voltage at said output node further comprises: an AND INVERT circuit having a first input, a second input, and an output wherein said first input of said AND INVERT circuit is connected to said output node and said second input of said AND INVERT circuit is connected to said control input node; a second P channel metal oxide semiconductor field effect transistor having a source, a gate, a drain, and an isolation well wherein said gate of said second P channel metal oxide semiconductor field effect transistor is connected to said output of said AND INVERT circuit and said drain of said second P channel metal oxide semiconductor field effect transistor is connected to said output node; a third P channel metal oxide semiconductor field effect transistor having a source, a gate, a drain, and an isolation well wherein said drain of said third P channel metal oxide semiconductor metal oxide semiconductor field effect transistor is connected to said source of said second P channel metal oxide semiconductor field effect transistor and said source of said third metal oxide semiconductor field effect transistor is connected to said first voltage supply node; a fourth P channel metal oxide semiconductor field effect transistor having a source, a gate, a drain, and an isolation well wherein said source of said fourth metal oxide semiconductor field effect transistor is connected to said first voltage supply node, said drain of said fourth P channel metal oxide semiconductor field effect transistor is connected to said isolation well of said second P channel metal oxide semiconductor field effect transistor, and said isolation well of said fourth P channel metal oxide semiconductor field effect transistor is connected to said drain of said third P channel metal oxide semiconductor field effect transistor; a fifth P channel metal oxide semiconductor field effect transistor having a source, a drain, a gate, and an isolation well wherein said drain of said fifth P channel metal oxide semiconductor field effect transistor is connected to said gate of said third P channel metal oxide semiconductor field effect transistor and the gate of said fourth P channel metal oxide semiconductor field effect transistor, said gate of said fifth P channel metal oxide semiconductor field effect transistor is connected to said control input node, and said source and said isolation well of said fifth P channel metal oxide semiconductor field effect transistor are connected to said output node; and a third N channel metal oxide semiconductor field effect transistor having a source, a drain, a gate, and an isolation well wherein said drain of said third N channel metal oxide semiconductor field effect transistor is connected to said gate of said third P channel metal oxide semiconductor field effect transistor and the gate of said fourth P channel metal oxide semiconductor field effect transistor, said gate of said third N channel metal oxide semiconductor field effect transistor is connected to said control input node, and said source and said isolation well of said third N channel metal oxide semiconductor field effect transistor are connected to said reference voltage node.

Claim 15

The voltage pull up circuit of claim 11 wherein said first voltage level is about 3.3 volts.

Claim 16

The voltage pull up circuit of claim 11 wherein said output voltage level is between about 0 and 5.0 volts.

Claim 17

The voltage pull up circuit of claim 11 wherein said reference voltage level is about zero volts.

Claim 18

The voltage pull up circuit of claim 11 wherein said critical voltage is about 2.0 volts.