US5488326A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data output circuit for semiconductor integrated circuit device which prevents current flow from the output to supply voltage
Assignee: Toshiba Corp
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Filing: 1994-04-06
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Granted: 1996-01-30
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Expires: 2014-04-06
Abstract
Abstract A data output circuit includes a P-channel transistor having a source connected to a supply voltage terminal V DD and a gate coupled to receive a drive signal from an internal circuit, and an N-channel transistor having its drain connected to the drain of the P-channel transistor and its source connected to an output terminal D out . The threshold voltage of the N-channel transistor is fixed to be lower than the thresholds of other N-channel transistors formed on the same substrate. A high level signal is output from the output terminal D out when a voltage output by the supply voltage terminal V DD is supplied to the output terminal D out through the P-channel transistor and the N-channel transistor. In this configuration; the output terminal charges quickly using the high driving capability of the N-channel transistor. Since the N-channel transistor is interposed along the current path from the output terminal to the supply voltage terminal, current does not flow from the output terminal to the supply voltage terminal when a voltage higher than the supply voltage is applied to the output terminal.
Inventors
- 👤 Sumako Shiraishi
- 👤 Masami Masuda
- 👤 Kazutaka Nogami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 15:14
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0008; H03K19/0013; H03K19/01; H03K19/017; H03K19/01707; H03K19/01721
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
195 words
A data output circuit, comprising: an internal circuit for outputting a first drive signal and a second drive signal; a P-channel transistor having a first end connected to a first supply voltage terminal and a gate receiving a signal obtained by inverting the first drive signal; a first N-channel transistor having a first end connected to a second end of said P-channel transistor, a second end connected to an external output terminal, and a gate receiving the first drive signal; and a second N-channel transistor having a first end connected to the external output terminal, a second end connected to a second supply voltage terminal, and a gate receiving the second drive signal, wherein a threshold voltage of said first N-channel transistor is lower than that of said second N-channel transistor, and when the first drive signal becomes high level and the second drive signal becomes low level, said P-channel transistor and said first N-channel transistor are turned on and said second N-channel transistor is turned off, so that a high-level voltage supplied from the first supply voltage terminal is outputted to the external output terminal through said P-channel transistor and said first N-channel transistor.
Claim 2
Dependent Claim
195 words
A data output circuit, comprising: an internal circuit for outputting a first drive signal and a second drive signal; a P-channel transistor having a first end connected to a first supply voltage terminal and a gate receiving a signal obtained by inverting the first drive signal; a first N-channel transistor having a first end connected to a second end of said P-channel transistor, a second end connected to an external output terminal, and a gate receiving the first drive signal; and a second N-channel transistor having a first end connected to the external output terminal, a second end connected to a second supply voltage terminal, and a gate receiving the second drive signal, wherein a threshold voltage of said first N-channel transistor is lower than that of said second N-channel transistor, and when the first drive signal becomes high level and the second drive signal becomes low level, said P-channel transistor and said first N-channel transistor are turned on and said second N-channel transistor is turned off, so that a high-level voltage supplied from the first supply voltage terminal is outputted to the external output terminal through said P-channel transistor and said first N-channel transistor.
Claim 3
Dependent Claim
268 words
A data output circuit for a semiconductor integrated circuit device comprising: an internal circuit for outputting a first drive signal and a second drive signal; a first N-channel transistor having a first end connected to a first supply voltage terminal, a second end connected to an external output terminal, and a gate receiving the first drive signal from said internal circuit; a second N-channel transistor having a first end connected to the external output terminal, a second end connected to a second supply voltage terminal, and a gate receiving the second drive signal from said internal circuit; a P-channel transistor having a first end connected to the first supply voltage terminal and a gate receiving a signal obtained by inverting the first drive signal; and a third N-channel transistor having a first end connected to a second end of said P-channel transistor, a second end connected to the external output terminal, and a gate connected to the first supply voltage terminal, wherein a threshold voltage of said third N-channel transistor is lower than those of said first and second N-channel transistors, and when the first drive signal becomes high level and the second drive signal becomes low level, said first N-channel transistor and P-channel transistor are turned on and said second N-channel transistor is turned off, and said third N-channel transistor is in an on-state, so that a high-level voltage supplied from the first supply voltage terminal is output to the external output terminal through said first N-channel transistor, and a voltage at the external output terminal is raised by said P-channel transistor and said third N-channel transistor.
Claim 4
Dependent Claim
268 words
A data output circuit for a semiconductor integrated circuit device comprising: an internal circuit for outputting a first drive signal and a second drive signal; a first N-channel transistor having a first end connected to a first supply voltage terminal, a second end connected to an external output terminal, and a gate receiving the first drive signal from said internal circuit; a second N-channel transistor having a first end connected to the external output terminal, a second end connected to a second supply voltage terminal, and a gate receiving the second drive signal from said internal circuit; a P-channel transistor having a first end connected to the first supply voltage terminal and a gate receiving a signal obtained by inverting the first drive signal; and a third N-channel transistor having a first end connected to a second end of said P-channel transistor, a second end connected to the external output terminal, and a gate connected to the first supply voltage terminal, wherein a threshold voltage of said third N-channel transistor is lower than those of said first and second N-channel transistors, and when the first drive signal becomes high level and the second drive signal becomes low level, said first N-channel transistor and P-channel transistor are turned on and said second N-channel transistor is turned off, and said third N-channel transistor is in an on-state, so that a high-level voltage supplied from the first supply voltage terminal is output to the external output terminal through said first N-channel transistor, and a voltage at the external output terminal is raised by said P-channel transistor and said third N-channel transistor.
Claim 5
Dependent Claim
258 words
A data output circuit for a semiconductor integrated circuit device comprising: an internal circuit for outputting a first drive signal and a second drive signal; a first N-channel transistor having a first end connected to a first supply voltage terminal, a second end connected to an external output terminal, and a gate receiving the first drive signal from said internal circuit; second N-channel transistor having a first end connected to the external output terminal, a second end connected to a second supply voltage terminal, and a gate receiving the second drive signal from said internal circuit; a P-channel transistor having a first end connected to the first supply voltage terminal and a gate receiving a signal obtained by inverting the first drive signal; and a third N-channel transistor having a first end connected to a second end of said P-channel transistor, a second end connected to the external output terminal, and a gate receiving the first drive signal, wherein a threshold voltage of said third N-channel transistor is lower than those of said first and second N-channel transistors, and when the first drive signal becomes high level and the second drive signal becomes low level, said first and third N-channel transistors and P-channel transistor are turned on and said second N-channel transistor is turned off, so that a high-level voltage supplied from the first supply voltage terminal is output to the external output terminal through said first N-channel transistor, and a voltage at the external output terminal is raised by said P-channel transistor and said third N-channel transistor.
Claim 6
Dependent Claim
258 words
A data output circuit for a semiconductor integrated circuit device comprising: an internal circuit for outputting a first drive signal and a second drive signal; a first N-channel transistor having a first end connected to a first supply voltage terminal, a second end connected to an external output terminal, and a gate receiving the first drive signal from said internal circuit; second N-channel transistor having a first end connected to the external output terminal, a second end connected to a second supply voltage terminal, and a gate receiving the second drive signal from said internal circuit; a P-channel transistor having a first end connected to the first supply voltage terminal and a gate receiving a signal obtained by inverting the first drive signal; and a third N-channel transistor having a first end connected to a second end of said P-channel transistor, a second end connected to the external output terminal, and a gate receiving the first drive signal, wherein a threshold voltage of said third N-channel transistor is lower than those of said first and second N-channel transistors, and when the first drive signal becomes high level and the second drive signal becomes low level, said first and third N-channel transistors and P-channel transistor are turned on and said second N-channel transistor is turned off, so that a high-level voltage supplied from the first supply voltage terminal is output to the external output terminal through said first N-channel transistor, and a voltage at the external output terminal is raised by said P-channel transistor and said third N-channel transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-29 | 1999-07-31 | 2000-01-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-29 | 2003-07-31 | 2004-01-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-29 | 2007-07-31 | 2008-01-30 | $7700.00 | Window Closed / Lapsed |